Designer’s Guide Community

Pavel

Senior Member

Offline

Posts: 174
Lausanne/Switzerland

comparator modelling - error during simulation
Apr 22^nd, 2008, 4:59am

Hello,

Here is AMS-model of comparator:
Code:

module COMPAR_v0 (INP, INN, OUT);
input INP, INN;
output OUT;
reg OUT;
electrical INP, INN;

initial begin
	if (V(INP)>V(INN)) OUT = 1;
	else OUT = 0;
end

always @(cross(V(INP)-V(INN),+1)) OUT = 1;
always @(cross(V(INP)-V(INN),-1)) OUT = 0;

endmodule

At the picture below there are waveforms.
Comparator output is connected to comp signal.
INP is connected to envlp, INN - to dac_out.
As you can see at the picture, after 2nd transition ('0'->'1'), output is frozen at '1'.
How to avoid this problem.

Thanks.

Pavel.

Back to top

COMPARATOR_coding_problem.jpg

IP Logged

Stefan Senior Member Offline Posts: 124	Re: comparator modelling - error during simulation Reply #1 - Apr 22^nd, 2008, 6:42am Maybe this is a timing issue of the solver. Try to set max timestep or use an appropriate $bound_step in your model.
Back to top	IP Logged

Pavel

Senior Member

Offline

Posts: 174
Lausanne/Switzerland

Re: comparator modelling - error during simulation
Reply #2 - Apr 22^nd, 2008, 7:27am

Thank you for response, Stefan

I can't use $bound_step as I have no analog costruction in this configuration.
Finally I resolved the problem. Here is code that works:
Code:

real OUTa;

initial begin
	if (OUTa > 0) OUT = 1;
	else OUT = 0;
end

always @(cross(OUTa,+1)) OUT = 1;
always @(cross(OUTa,-1)) OUT = 0;

analog begin
	@(initial_step) begin
		if (V(INP)>V(INN)) OUTa = 1;
		else OUTa = -1;
	end
	@(cross(V(INP)-V(INN),0))
	;
	if (V(INP)>V(INN))
		OUTa = 1;
	else OUTa = -1;
end

Regards.

Pavel.

Back to top

IP Logged

Stefan

Senior Member

Offline

Posts: 124

Re: comparator modelling - error during simulation
Reply #3 - Apr 22^nd, 2008, 7:37am

Hi Pavel,
your code generally does the same as the $bound_step function would do.
It makes the analog solver produce an calculation closer to the crossing, so that it can be detected from the digital part.
If you use wavescan to plot your first grafic you might see that there is no analog waveform crossing at the second falling edge.
Can you confirm that ?
There should be a better way to make a working code than your (well working, but pretty difficult to read) code.

Regards,

Stefan

Back to top

IP Logged

Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: comparator modelling - error during simulation Reply #4 - Apr 22^nd, 2008, 2:35pm Try tightening the tolerances on the cross functions. -Ken
Back to top	IP Logged

jbdavid

Community Fellow

Offline

Posts: 378
Silicon Valley

Re: comparator modelling - error during simulation
Reply #5 - Aug 27^th, 2008, 1:10am

or try writing it as a single cross statement with tolerances

initial OUT = V(INP,INN) > 0;
always @(cross(V(INP,INN),0,vtol,ttol)) OUT = V(INP,INN) > 0;

But you do need a decent circuit feeding you INP and INN
or you won't get enough timesteps on the analog side anyway..

above is an interesting function to look at too.

Back to top

jbdavid
Mixed Signal Design Verification

IP Logged

jbdavid

Community Fellow

Offline

Posts: 378
Silicon Valley

Re: comparator modelling - error during simulation
Reply #6 - Aug 27^th, 2008, 1:19am

your working model is effectively
initial OUT = V(INP,INN) >0;
always @(cross(OUTa)) OUT = OUTa >0;
analog OUTa <+ (V(INP,INN) >0)? 1:-1;
endmodule

so the cross statement in the analog block only forces a timestep at the crossing, but equation (not inside the cross) ALSO forces a timestep there because of its discontinuous nature (which is probably going to cause a problem in a larger simulation. )

Back to top

jbdavid
Mixed Signal Design Verification

IP Logged