Designer’s Guide Community

‹ Previous topic | Next topic ›

Pages: 1

Setup simulation for SCL MOS divider (Read 1772 times)

vkale

New Member

Offline

Posts: 2

Setup simulation for SCL MOS divider
Apr 22^nd, 2008, 7:09am

Hi,

I have a SCL(or CML) divider with fclk=1.5GHz and i would like to simulate in order to get the half of the clock freq. I have set the current to a value that allows to operate the transistors at the expected frequency. But I can't get the right waveform. Is there anything about Spectre(some initial condition thai I must set), or is something else?

Bill

IP Logged

ACWWong

Community Fellow

Offline

Posts: 539
Oxford, UK

Re: Setup simulation for SCL MOS divider
Reply #1 - Apr 22^nd, 2008, 2:06pm

if your SCL divide-by-2 is designed correctly and you drive the input at fclk then you should get fclk/2 at the output. There is no need for initial conditions in Spectre transient analysis to simulate this. If it doesn't work, then you have a problem with the design or setup which will not be corrected by initial conditions. More details would be needed for a better diagnosis.

IP Logged

Pages: 1

‹ Previous topic | Next topic ›