I am writing a current limiter in Verilog-A. Should be simple but in simulation the results are not as expected. Any suggestions will be appreciated.

`include "discipline.h"
`include "constants.h"

module current_limiter(in,out);
inout in, out;
current in,out;
parameter imax = 100e-3;

analog
begin
  @(initial_step)  if (I(in,out) > imax) I(in,out) <+ imax;


end
endmodule



Thanks.

Stefan, Thank you. But adding "if (I(in,out) > imax) I(in,out) <+ imax; " does also not work.

module current_limiter(in,out);
inout in, out;
current in,out;
parameter imax = 100e-3;

analog
begin
  @(initial_step)  if (I(in,out) > imax) I(in,out) <+ imax;

if (I(in,out) > imax) I(in,out) <+ imax;

end
endmodule

The problem is more subtle than that. To build a reliable current limiter you cannot simply compare the output current against Imax, and then if above Imax, set the output current to Imax. Once you override the output current, it is no longer over Imax. This results in the state switching back and forth between limiting and not limiting on every iteration, which would cause convergence problems. A robust model can be found in the Verilog-AMS section of this site (www.verilog-ams.com). It is called "Current limited voltage regulator" and can be found in the functional Verilog-A models section.

-Ken