guerreiro wrote on Jun 5th, 2008, 2:51pm:Hello Designers,
I'm designing an SAR ADC and I've done some noise analysis of the dynamic comparator I'm using. The problem is that the input-referred noise has a sigma equal to 750uV (Gauss distribution), while the LSB is about 977uV. In this case the amplitude of the noise is very large, when compared with value of the LSB. Is there any way to reduce the input-referred noise of the comparator, other than using a preamplifier?
Thanks
Guerreiro
Hi,
You might want to consider a modification to your SAR scheme by building in some redundancy. This will allow you to tolerate an enormous amount of error in the comparator. I think this should eliminate comparator noise as a serious issue altogether.
Of course, this will come at the cost of 1-2 more conversion steps depending on how you implement this redundancy. There are probably several different methods to implement this, but one that comes to my mind immediately is by F. Kuttner from ISSCC 2002 - A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS.
This paper presents a very elegant solution to what is a very difficult problem otherwise. Alternatively, you may consider using a cyclic ADC instead of a SAR ADC where digital redundancy can be built in very easily, and you also have several other degrees of freedom. Of course, you probably need more power.
Best regards,
Vivek