Hello Designers,

I'm designing an SAR ADC and I've done some noise analysis of the dynamic comparator I'm using. The problem is that the input-referred noise has a sigma equal to 750uV (Gauss distribution), while the LSB is about 977uV. In this case the amplitude of the  noise is very large, when compared with value of the LSB. Is there any way to reduce the input-referred noise of the comparator, other than using a preamplifier?


Thanks


Guerreiro

Hi Guerreiro,

I agree with Yawei: The offset of dynamic comparators is large (unless you use a kind of calibration).
Noise is therefore usually not of concern (since it is small compared to the the offset).
If your LSB is 1mV I suggest to use a structure with a preamplifier-stage.

Cheers

Hi Guerreiro,

I think that you will need a preamp, and a well-designed one if you are facing noise problems in it. From what you suggest, I think you are seeing more white noise and
not just 1/f noise, so chopping etc. would not really help.

Also, use a fully differential comparator for your SAR if you aren't already doing this. Ditto for your ADC. This will double the signal range relaxing noise requirements by
3 dB (noise power up by 3 dB in differential design and signal power up by 6 dB).

If you are not using a preamp simply for saving power, then you might want to consider architectural modifications to your SAR like self-timed comparators where you do not need to burn as much power in the preamp is in the default SAR design.

Most importantly, whatever you do, first also try to optimize your basic comparator input stage for noise. This is an oft forgotten point.

Regards
Vivek

Thanks to ALL !!!

I'm already using a preamp to reduce the noise, but didn't do much about the comparator. Now, my problem is the power required by the preamp.
I made some calculations and found that it is needed about 9 V/V of DC gain. Once I have a 1V power supply,    I'm using a 2 stage preamp and I can't design the preamp with active load. Instead of that I'm using resistors.

I will see now the methodology outlined
in the "Simulating Switched-Capacitor Filters with SpectreRF" and find out if it is possible to reduce the requirements of the preamp, reducing the input-refered noise of the comparator.


Once again, thanks for your suggestions.


Guerreiro

guerreiro wrote on Jun 5^th, 2008, 2:51pm:


Hi,

You might want to consider a modification to your SAR scheme by building in some redundancy. This will allow you to tolerate an enormous amount of error in the comparator. I think this should eliminate comparator noise as a serious issue altogether.

Of course, this will come at the cost of 1-2 more conversion steps depending on how you implement this redundancy. There are probably several different methods to implement this, but one that comes to my mind immediately is by F. Kuttner from ISSCC 2002 - A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS.

This paper presents a very elegant solution to what is a very difficult problem otherwise.  Alternatively, you may consider using a cyclic ADC instead of a SAR ADC where digital redundancy can be built in very easily, and you also have several other degrees of freedom. Of course, you probably need more power.

Best regards,

Vivek