Having mismatched impedances becomes a mess if you have any reflections (i.e., long transmission lines between blocks).  Assuming thatn's not the case, and you're talking about interfaces between blocks on-chip (distances small enough for reflections and other EM effects not playing a role), I would probably start using voltages/currents/impedances instead of powers, to be able to account for the mismatched impedance effects.  In addition to dBm, IIP3 (and related metrics) can be converted into dBV (using a volt as the reference instead of milliwatt); this tends to make it easier to work with on-chip cascade calculations.  Overall, as soon as I get on-chip, I would convert all powers into voltages, and all gain stages into transconductance stages, and start calculating voltage gains instead of power gains.

Excellent question - let me think about it a bit... It's been a while since I did receiver calculations.

Overall, when impedances get mismatched, simple gain/IIP3/1DBCP/NF calculations that ignore impedances no longer work.  At that point, I remember switching to voltage/current/impedance calculations.  I wonder what the easiest way to model everything would be... maybe Zin/Gm/Zout/Nin,v/Nout,i?  Using voltage/current gains voltage/current noises are equivalent, perhaps it would be most effective to analyze inputs with voltages and outputs as currents, using transconductances as the gain elements...?  I'm thinking all of this from CMOS point of view; with HBTs it might be easier to consider current all the way...

But for a generic approach, yes - the exact impedance of the previous stage matters.  I remember seeing excel calculation sheets online that incorporated everything in them (impedances at both ends of interface, input/output-referred current/voltage noise sources, input/output referred linearity...).

But to answer your questions: the generic approach is to model input referred noise as noise current and noise voltage, and  define the impedances.  In the calculation spreadsheets you would know what the impedance of the previous stage is - all input and output impedances would have to be included and tracked to account for the mismatched impedances.  It won't be that bad, though - it's just a bunch of equations that can be derived in a pretty straight forward way (although it takes some work).

Anyways, good luck with either 1) finding an spread sheet that covers all this, or 2) building one yourself.


I wonder if the best way to model everything in the calculation


Simulation?

The answer is "no" for noise, but "yes" for gain/IIP3 if you know the impedances.

The problem with mismatched impedances is that NF, IIP3 and gain are all (usually) defined based on 50-ohm impedance levels.  If you change the impedances, these numbers will change.  So, for your cascaded NF/IIP3/gain calculations, you really need to know the impedance levels everywhere if you want to use the performance metrics of the individual stages.  Once you know the impedances, you can calculate gain and IIP3 relavitely easily.

For gain, you can calculate the voltage gain from the power gain.  Probably the easiest way to do this is to model your block as a 50-ohm input impedance, and a voltage-controlled voltage source (gain stage) with a 50-ohm output impedance in series with it.  The power gain number is (almost) always assuming that the input impedance of the next stage is 50 ohms ("maximum power transfer").  Therefore, a 50/50 voltage division cuts the input voltage of the next stage in half when compared to the output of the VCVS device.  And, since power gain Ap=Av^2, your Avcvs=2*SQRT(Ap).

However, if you change the input impedance of the next stage, this affects the input voltage it sees because the voltage division ratio changes.  Maximum gain would occur if the next stage has an infinite impedance (reasonable assumption for CMOS inputs at low frequencies); in this case the voltage gain would be 2x of what it would be for a 50ohm-50ohm matched condition.  Similarly, if the input impedance of the next stage is less than 50 ohms, your voltage gain would decrease from the 50ohm-50ohm case.


Then, IIP3 is an extrapolated measure of linearity, referring to an input power that would make the extrapolated 1st harmonic and extrapolated 3rd harmonic (caused by nonlinearities)  to be equal.  This can be converted into a voltage as well.  IIP3 input power level can be converted into a IIP3 voltage level with the simple equation Viip3=50ohms*SQRT(Piip3).  Once IIP3 is converted into voltage, you can use voltage gain values (that take into account the mismatched impedances) to determine the cascaded voltage IIP3.



Noise is trickier.  Input-referred noise is modeled as two input noise sources - one a current noise source, and the other one a voltage noise source.  Noise Figure is calculated assuming a 50-ohm source impedance, using the equation NF=(Ns+Na)/(Ns) where Ns is the noise of an ideal 50-ohm resistor, and Na is the noise added by the circuit, referred to the input).  Since the source impedance is known, the effects of both the voltage and the current noise sources can be calculated and lumped together as a single number, "Noise Figure".  However, this breaks if the source impedance changes - the voltage and current noise sources generate different amounts of noise depending on the impedance.  To determine noise accurately, you need to know what the current and voltage noise sources are, and NF doesn't tell you that.

So, in a situation where you use a generic LNA with NF/IIP3/Gain values but change the source impedance, you can calculate IIP3 and gain, but NF you don't really know.  If you can measure the LNA, you can short the input to an AC ground to see what the voltage noise is and leave it open to see what the current noise is (similar techniques are used to switch between Norton and Thevenin equvalent circuits).  If not, there's little you can do.

Advanced approach: modeling all the noise with a single voltage noise source in CMOS circuits.  If you had a pure CMOS input stage, you could model the input having a 50-ohm resistance to ground, and model the noise using a voltage noise source between the 50-ohm resistor and the actual input of the amplifier that would have an infinite input impedance (i.e., the input impedance is moved to be outside the ideal amplifier).  This is opposed to a more traditional way of having the input impedance between the current/voltage noise sources and the amplifier input.  In a CMOS case, this approximation may yield reasonable results since the gate input impedance is pretty much an open circuit (at least at low frequencies).  Then, determine the value of the voltage noise source based on Noise Figure, 50-ohm input impedance and an assumed 50-ohm source impedance.  Once you have that, you can calculate the generated noise in any impedance condition.  Note that this is an approximation, and depending on the circuit, it might give you incorrect results (but then again so could any other approach if all you know is NF and your impedances are mismatched).