Hi Guys,
I am facing some problem in comparator design.I want a (1-2)ns and low slew(<300ps) comparator.For that purpose i have designed one cascaded differential amplifier(first 3 stages) connected to a level converter and then final inverter.Supply is 1.2V and 0.13um process.The delay and slew i get for this is 3.2 ns and very large slew(~1ns).Each differential amplifier consumes around 20uA.So can u suggest some better solution for my design.Does a preamplifier help in this case??pls reply soon...

Here slew means the output changesfrom logic lo to hi or hi to lo in that time .So essentially output takes that much time to change from one logic to other..traditionally it os defined as time to reach from 10% to 90% of the signal.

Hi Jiesteve,
Lot of thanks for ur help,my circuit has worked.But i have some questions:i have used minimum length devices,and for low gain topology i have used higher overdrive devices(Vdsat),so it increases the current without changing the size,thus improve the speed.But menwhile the power is consumed ,how to minimise the power consumption in this case??