Hi Aaron,

you should be able to "extract" the capacitance of your LO line and put it back into the simulation. This is also true for the resistance and inductance using tools like Assura etc.

anyway you should use higher/top level metals far from substrate and minimise other metals crossing... i don't see a problem with 0.4um * 0.5mm length if properly extracted and accounted for, but what I would say is that if the track was say 0.8um wide, then roughly the resistance would half, but the capacitance would only increase by say 33% and not double because fringing capacitance should be dominate over bottom plate capacitance for such a thin line.

cheers
aw