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How to increase switch off resistance? (Read 5001 times)
manodipan
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How to increase switch off resistance?
Jun 10th, 2008, 10:36pm
 
Hi Guys,
I have designed some switches having some Ron and Roff specs.Now the problem is to get sufficient Ron(~1K) i get very low off resistance (~1M)leaking lot of current.Now i want to increase the off resistance not degrading the Ron too much.Right now i have switch with Ron=13K and Roff =8M.How to make it better??i look forward to ur help..
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vivkr
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Re: How to increase switch off resistance?
Reply #1 - Jun 10th, 2008, 11:06pm
 
Ron = 13 k vs.  Roff = 8 M? That looks quite bad. Hopefully, there was no typo there. What technology is this?

In general, the Ron vs. Roff tradeoff is quite hard and there are probably very few possibilities for you. Some that I can think of:

1. Increase channel length (L). This reduces Ron but usually Roff improves dramatically with just a slight increase in L, and the required increase in W is tolerable then.

2. Manipulate the gate control signal. You could try using an NMOS device with gate voltages > VDD for ON state and < VSS voltages for OFF state.
Basically, use just an NMOS device, and set the gate to -0.4 V or so in OFF state (careful not to turn any parasitic diodes ON or you are in for trouble).

3. The ON part is harder. You could use a 2.0 V or even 2.5 V to turn the NMOS ON giving you good Ron but then your gate oxide is likely to suffer. The best
solution is to use bootstrapping in ON mode. There are plenty of examples out there. Look for the JSSC paper by M. Dessouky & A. Kaiser (March 2001).
This way, V(G) is much larger than VDD, can be upto VDD, but V(G,S) is always less than VDD.

4. The -0.4 V for OFF state can be generated with a chargepump. Again, be careful to make sure that you are not overstressing the gate. Check your peak input signal
to the switches to make sure that V(G,S) and V(G,D) are always < absolute max. ratings.

Hope this helps.

Vivek
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manodipan
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Re: How to increase switch off resistance?
Reply #2 - Jun 11th, 2008, 2:13am
 
Hi Vivek,
Thanks a lot for ur elaborate help.I did one mistake,i connected NMOS body to source and was getting low off resistance.Now body is grounded and source is at fixed voltage,and i am getting Ron=1.4K and Roff=107M.MOS length is minimum and technology is 0.13u UMC.actually increasing length requires width increase which in turn increases charge injection and clock feedthrough which i dont want.I am planning to bootstrap gate for varying input signal at source to counter nonlinear resistance.Is that ok?it will be great if u reply??thanks...
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vivkr
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Re: How to increase switch off resistance?
Reply #3 - Jun 12th, 2008, 2:35am
 
Hi manodipan,

Nice to know that you were able to fix your problem so easily.

As for bootstrapping, I would recommend it if linearity is critical for you, i.e. you are either working with very low supply voltages, or
if you need very good linearity for a very rapidly changing signal. You can check out the JSSC paper I mentioned in my earlier post.

I see the following pros and cons:

Pros:
-----
1. Excellent linearity achievable, especially for very high frequency input signals.

2. Main switch device very small (simple NMOS).

3. Charge-injection etc. are also good, largely signal-independent, one more reason for the excellent linearity.

Cons:
-----
1. Bootstrap capacitance needs to be large. For low VDD, I would say that Cbootstrap ~ 4-5*Cgate is needed, where Cgate is the gate cap of the main MOS switch.
This runs into area.

2. Parasitics must be reduced well, especially parasitics from the assisting switches. See Fig. 7 (I think it is Fig. 7 of the paper). The more parasitics you have there, the
lower will be the V(G,S) of the main switch. It never will be VDD anyway.

3. You always need a running clock as the bootstrap is dynamic. This is not a problem in most cases, but can be if you are trying to make an ADC which operates in burst-mode, i.e. the ADC lies dormant and may not even receive any clock, but suddenly the CLK is enabled and a CONVERT signal is asserted, following which the ADC must quickly produce an output.
Mostly, there is the additional requirement that the ADC "passively" sample a rather rapidly varying input signal while it is dormant. However, as I said, this is happily not often the case.

Other points:
-------------
1. I would advise using as few bootstrapped switches as possible. Delta-sigma modulators are the best place to use these as you usually only have 2 inputs and need 4 bootstrapped switches. Pipelined ADCs actually benefit from these switches a lot, but you might need several of these there, depending on your design.

2. If your input signal varies very fast, make sure that you use a bootstrapped switch on both sides of the cap, the signal side (floating side) but also on the other end, which is usually tied to a common-mode potential, otherwise your linearity will be poor.

3. For the same reason as listed above, do not try to sample a rapidly varying input signal on a cap, the other end of which is tied to an opamp-controlled virtual ground node in the sampling phase.

4. If you happen to have too many signal branches going into your circuit, requiring several bootstrapped switches, it might be worth considering the use of a dedicated sample-and-hold amplifier upfront. You can realize some gain in it also. This way, you save the area you would otherwise be spending for those huge bootstrap caps.

Vivek
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Re: How to increase switch off resistance?
Reply #4 - Jun 16th, 2008, 1:06pm
 
all good advice from Vivek.

One other trick - If you are trying to increase Roff of the switch to minimize signal feedthru of the switch, use two switches in series, and a third switch between the two to ground.

When switches feed thru, ground switch is open, and

when the two switches are in series and turned off, the ground switch is turned on and kills (or greatly reduces) the parasitic feedthru of the switches.
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