manodipan wrote on Jun 11th, 2008, 3:39am:In SC filter design we generally design one continuous time Opamp based circuit first from the filter specs(passband gain,stopband rejection etc.),then convert each resistors by switched capacitor and the assumption is that clock frequency>>signal frequency.So that in technical terms is kind of oversampling the signal,which i don't want to do always.In the case of clock frequency close to signal bandwidth or in case Bandpass filter of high center frequency where the requirement dictates very high clock frequency how to design the SC filter??
1,) It is the great advantage of S/C filter design that structures often are even simpler than RC topologies (for example: positive or difference integrator to be realized only by proper switch phasing,without equivalence to the time continuous case). Therefore, simple resistor replacement is not always economic.
2.) The clock frequency has to be always larger to the pole frequency of the filter - at least by a factor of 50 (normally: 100...200). Otherwise, the formulas for resistor-capacitor equivalence cannot be applied.
And more than that, there is a large distortion of the filter transfer curve for low ratios clock-to-frequnecy.
For example: Resistor replacement by the EULER approximation leads to infinity at f=f,clock.
This can be corrected more or less by the S/H action of the last stage - but this creates the typical sinx/x distortion.
In short: Low clock rate leads to more distortions and deviations from the desired response.
3.) If the clock-to-frequnecy ratio is low, it is very difficult to remove the clock signals from the output. For a ratio which is sufficient high an addtional time continuous filter often is not needed.
4.) SUMMARY: Donīt use a clock rate which is too low. Your filter cannot work properly.