cmos_cowboy
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Just to clarify. It is a digital type divider. All I am interested in doing at the moment is trying to work out the divider phase noise not the full PLL. The divide values are large but the output is re-timed so I can reduce simulation time by reducing the divider value as only the front-end and sampler add jitter. Hence the ouput frequency is higher that it would be in reality. I can measure the edge-to-edge jitter of the ouput clock and plot it in the time domain. However if say any periodic ripple is added to the supply, at a frequency that is not harmonically related to the output clock then this modulate the ouput and cause a spur. I can take a pk-pk or rms of the Jee I record, this data is obviously periodic (at what will be the spur frequency) so only one period is required. I dont think it is correct to try and convert this to phase noise in the ususual way (PN=20log(Jee_in_rads)) as it is not a gaussian distribution. So how do I do it?
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