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The Designer's Guide Community Forum › Modeling › Behavioral Models › behavioural modelling of a VCO for phase noise using Verilog -A
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behavioural modelling of a VCO for phase noise using Verilog -A (Read 570 times)
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behavioural modelling of a VCO for phase noise using Verilog -A
Jul 21st, 2008, 1:59am  
Hi,
I am a new commer to he field of analog behavioural modeling.Presently i am trying to model a VCO that can give the phase noise..But i am really confused how to impliment this phase noise part.Is any body have the code for this please help me.....Thanks in advance.. Smiley
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Re: behavioural modelling of a VCO for phase noise using Verilog -A
Reply #1 - Jul 21st, 2008, 2:03am  
Check the model section of this website.
Basically, you just randomly vary the period of the oscillator with a specific variance to reach the specified power level at the frequency offset.
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