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how to simulate spectreVerilog from command line? (Read 2046 times)
Antara
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how to simulate spectreVerilog from command line?
Jul 31st, 2008, 6:42am
 
Hi all,
        I am facing problem while running spectreVerilog from command line. When simulation is done through cadence's analog environment window an executable file called runSimulation is obtained.
When this file is made to run from command line, the simulation is complete for spectre simulation, but it terminates for spectreVerilog after few steps, and 'segmentation faults' is shown in the command window.
      Please can any one tell me how to solve this problem.
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jbdavid
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Re: how to simulate spectreVerilog from command line?
Reply #1 - Aug 4th, 2008, 12:39pm
 
do you have a valid path to the verilog-xl or ncverilog executable with the verimix code compiled in? The first thing I would suspect in this situation is that the Verilog simulator is failing to start.. - ie you are running on solaris, but pointing to a linux executable for the verilog..
-- But I'm hoping that my last brush with this tool 4 years ago is my LAST one.. AMS is so much better!

jbd
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jbdavid
Mixed Signal Design Verification
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