Hi, I'm new to the site.

I'm currently creating a 10-b pipeline ADC using digital error correction (of course!) but am not 100% sure on how to combine the digital outs from each stage.

I am using the typical method, which is to take the MSB of the first stage, then add the LSB of the first stage and the MSB of the second stage, add the LSB of the second stage to the LSB of the third stage, and so on. This seems to work quite well, though to be perfectly honest, I am not so hot on WHY this works at all! I have read various papers and descriptions in books such as CMOS Data Coverters for Comms and Jacob Baker's books, but found it quite confusing.

My main issue is how to combine the last few bits, i.e. from the 8th pipeline stage and the 2 bits from the flash at the backend. The 8th pipeline stage is like the others; there are decision levels at +- Vref/4, but the flash is split up over the range equally into 4 segments. What I am currently doing is adding the LSB of the 8th stage to the MSB of the flash, and then using the LSB of the flash as the LSB of the entire converter. Is this the right thing to do? It's a bit hit and miss and if anybody could explain......?? There must be a simple explanation.

I've created a verilog-a model of the pipeline, but the flash outputs look a little dodgy. They depend on the output residue of the 8th stage and the time that this is not always 'equal' (the time it's high is not always the same as the time it is low for a ramp input to the ADC), meaning the flash outputs are not evenly spaced. I input a ramp to the ADC and look at the digital outs. But it only seems to work well if this is a slow ramp (if the ramp is fast, the LSB toggles when the residue goes from high to low or vice versa... and since this is not every clock cycle, the LSB pulses can be larger than some of the other pulses, so it doesn't 'count' properly up the ramp). Perhaps I can explain that better if it's not been understood.

Anyway, thanks for any help!

Thanks for your reply.

I understand what you say, but perhaps I didn't make my question clear enough (sorry!). It's the combining of the bits that I'm unclear about, especially at the end with the flash. Is it the correct thing to do by adding the LSB of the eight stage to the MSB of the flash to get the 9th bit, and then taking the LSB of the flash as the LSB (10th bit) of the entire converter?
I find this confusing since the 1.5b stages split the range into -Vref to -Vref/4, -Vref/4 to Vref/4, and Vref/4 to Vref. However, the 2-b flash splits the range up equally, so can the LSB of the last 1.5-b stage be added to the flash MSB?

I understand about the residue and the offset the comparators can have (+- Vref/4), and that this introduces some redundancy. I've been doing this for a while now and have yet to find literature which gives a simple (or mathematical) explanation about the recombining of bits; I find it very confusing!

Yes, the Stephen Lewis paper, I have that saved somewhere. I will read it again and try to get my head round all of this. Thanks for your help, it is re-assuring to know that I am doing it the correct way, and so now I just have to sort out my other problems!

thomasross20 wrote on Aug 8^th, 2008, 3:55am:


He shows it in his PhD thesis... He "forgot" to put this key detail in his papers, i suppose.

BTW, Lewis proposal is not the one you are probably using. The most frequent implementation uses 2 comparators (set at +-Vref/4 for 1.5 bit stages) and RSD encoded levels, and was introduced by Jespers, Ginetti.

you might find my tutorial on modeling one of these at BMAS helpful..

BTW its NOT Digital Correction.. As Boris Murman would say.. you are just re-aligning and adding up the outputs bits.. Nothing "wrong" nothing "Corrected"  

Its not easy to get ones head around the first time..
the bmas website is at http://www.bmas-conf.org
See the Archives section for 2001
the tutorial lists a lot of the papers (available on IEEE Xplore) that
are associated with this topic.. of course simple google scholar search will find many of them for you too!

jbd