Hi, I'm new to the site.
I'm currently creating a 10-b pipeline ADC using digital error correction (of course!) but am not 100% sure on how to combine the digital outs from each stage.
I am using the typical method, which is to take the MSB of the first stage, then add the LSB of the first stage and the MSB of the second stage, add the LSB of the second stage to the LSB of the third stage, and so on. This seems to work quite well, though to be perfectly honest, I am not so hot on WHY this works at all! I have read various papers and descriptions in books such as CMOS Data Coverters for Comms and Jacob Baker's books, but found it quite confusing.
My main issue is how to combine the last few bits, i.e. from the 8th pipeline stage and the 2 bits from the flash at the backend. The 8th pipeline stage is like the others; there are decision levels at +- Vref/4, but the flash is split up over the range equally into 4 segments. What I am currently doing is adding the LSB of the 8th stage to the MSB of the flash, and then using the LSB of the flash as the LSB of the entire converter. Is this the right thing to do? It's a bit hit and miss and if anybody could explain......?? There must be a simple explanation.
I've created a verilog-a model of the pipeline, but the flash outputs look a little dodgy. They depend on the output residue of the 8th stage and the time that this is not always 'equal' (the time it's high is not always the same as the time it is low for a ramp input to the ADC), meaning the flash outputs are not evenly spaced. I input a ramp to the ADC and look at the digital outs. But it only seems to work well if this is a slow ramp (if the ramp is fast, the LSB toggles when the residue goes from high to low or vice versa... and since this is not every clock cycle, the LSB pulses can be larger than some of the other pulses, so it doesn't 'count' properly up the ramp). Perhaps I can explain that better if it's not been understood.
Anyway, thanks for any help!