Hello,

I'm trying to find a way of simulating the INL/DNL of a fully-differential pipeline ADC in Cadence, using spectre/verilog-A. There is an ahdl library with DNL/INL blocks, but these are single-ended and their operation not explained well. Any help on this matter would be appreciated. Note the pipeline has a delay time before it starts outputting correct data..

Secondly, several references are at odds when defining the DNL of an ADC. Is it related to the width of the analog input along the x-axis or the height of the digital transition on the y-axis? I would say the analogue width...

Thanks
I read the code a few times and it eventually made sense; I ended up writing my own version which drives the ADC with a differential input and non-overlapping clock, with an option to start the analysis after the initial delay
The only thing I'm having trouble with now is the CMFB for the gain-boosting amps; analogue design, don't you love it?