Hi all,
I want to automatically include the backannotated parasitic RLC in my schematic so that when I run different set of simulations I can see the exact performance.

I use Calibre PEX to extract RC and use Diva LVS to backannotate on the schematic. However Diva LVS only shows r,c as text on the lines. Then, I need to put the caps and resistors with these values from the analogLib. Repeating this process for every circuit is not efficient. Is there any way to bring extracted layout parasitics to the schematic as parasitic RLC elements automatically?

Any help is appreciated.
Thanks,
eng

Hi eng,

I am not sure if I understand your problem correctly.  

I don't run diva LVS to back annotate the parasitics onto the schematic. After Calibre PEX extracted all parasitics successfully, it pops up a window named Calibre View Setup. After I set up some parameters, it generates a schematic with all parasistics.

How do you run Calibre PEX? In Cadence ICFB environment all in UNIX shell? Would you please provide more details?


Yawei