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How to model a CT ADC? (Read 2870 times)

lightgo New Member Offline Posts: 6	How to model a CT ADC? Aug 18^th, 2008, 6:48pm Hi, I am a beginner of ADC, my aim is to implement a 12-bits 10M signal width CT ADC. Now, i am focus on ADC modelling. Who can give me some suggestion or recommend something usefule? :)Thanks.
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thomasross20 Junior Member Offline Posts: 30	Re: How to model a CT ADC? Reply #1 - Aug 19^th, 2008, 6:58am There are two main options nowadays; these are to use a mathematics program such as matlab or scilab to do your modelling, or to use verilg-a/ams; this allows you to write your own analog modules using code, but the license costs can be hefty.
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jbdavid

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Posts: 378
Silicon Valley

Re: How to model a CT ADC?
Reply #2 - Aug 27^th, 2008, 1:37am

Most ADC's are pretty useless if they are not clocked..
usually when I see CT in conjunction with ADC, there is the also the term ΔΣ in front of ADC .. is this the case..
if so the CT time part is really an integration stage or two.
so a verilog-A model is quite possible.
so you need to model the Summing Amp (because you have to add the input with the FEEDBACK DAC) the FEEDBACK DAC, the integration, and the "SLICER" or internal FLASH ADC..
I recommend starting with that flash ADC and the DAC's first..
once you have cut your modeling teeth on those.. you'll be ready to try your hand at the integration stuff..

jbdavid
Mixed Signal Design Verification

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Paul Community Fellow Offline Posts: 351 Switzerland	Re: How to model a CT ADC? Reply #3 - Sep 1^st, 2008, 1:09pm If you have access to Matlab, you can get started with the discrete-time Delta Sigma Toolbox by Richard Schreier. This will give you a good starting point and improve your understanding of SD ADCs. Regards, Paul
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