Hi all,
In general, error amplifier in LDO is one-stage amplifier and its output impedance is not very large, so the LDO's dominant pole is at LDO's output, not error amplifier's output, and a large capacitor (uF) at LDO's output is needed to reach it.

Why not use folded-cascode as error amplifier? It can make the amplifier's output be the dominant pole even there is pF capacitor at LDO's output. The advantage are:
1) no need large capacitor(uF) at LDO's output.
2) though the bandwidth is smaller, the larger loop gain can reach a better PSRR

Thanks!

Regards,
Trashbox

Hey buddypoor,

I consider using the compensation scheme from silva-martinez in a LDO implementation (without external cap).
Have you ever implemented a chip using this technique?
Can you give me some useful suggestions?

Thank a lot, regards

I think folded cascode error amp is a good choice. For the compensation one can use the good old miller cap across the big pass device.
But this is all when using a PMOS pass device.

Hi buddypoor,
Thanks for your reference. It seems good to produce a zero by VCCS instead of esr resistor.

Regards,
Trashbox

nano_RF wrote on Aug 20^th, 2008, 7:56am:



mmmm...the pass transistor stage does not usually have a large gain. Two reasons:

1) The LDO can work with such pass transistor in triode mode....
2) Even in saturation mode, the load is not large enough in order to provide a large (and constant) gain.

Therefore, I would not try to use a Miller compensation scheme across the pass transistor, but rather try to do it on the error amplifier if possible.

Regards
Tosei

Hello everybody,

Thinking a little bit I came to the conclusion that also the output impedance of the regulating amplifier might change substantially because a different vgs of the pass transistor (vs current, input voltage etc).
The dominant pole will therefore change, too.
Can there be something done to prevent that?

Cheers

no capacitor LDO is not easy realized, since for a LDO driving large current(mA level) , its output pole can drift in a very large range(several Hz to KHz), so usually we design the output as the dominant pole.

trashbox wrote on Aug 19^th, 2008, 7:56pm:

Hi,

[//quote author=engronger link=1219200978/0#13 date=1220538374]i am afraid not, you know the pass element device's gate has a big capacitance. and the cascode configuration's drive ability is not enough.//quote]

Thanks for your point. But I guess without knowing the real spec requirement this is open to as many configuration as you want.

(1) First of all one needs to choose NMOS or PMOS diff pair. PMOS input pair is usually the choice since your ramping voltage is reference to ground.

(2) Depending on what error voltage is allowed. Say if you want LDO output voltage to be withing such and such error voltage. this will determine the required open loop gain for your set up. And will contribute to your Error amp choice.

(3) Now how big a pass device you are using depends on the Load current , and RON requirement. If you become worried about slew rate, then I am afraid you may need to go for high slewing opamp as an error amp. In other words Class A-B kind of amplifier, which will ensure that you have same pushing and pulling ability. And do get a similar ramp up and ramp down performance.

(4) You will need to use a cap at LDO output to make it as a RF short assuming this LDO is essentially providing current for an RF amplifier.

(5) And not to mention that bandwidth of the loop is related to your ramping up and rampig down profile. You need to know this spec as well.

(6) The RC corner of the Vramp input is also need to be set such that it is not passing the noise at the LDO output which will directly appear as noise at the loaded amplifier output. And depending on the number of stages this LDO is connected to can have AM and PM noise component as well.

This is a healthy discussion. Please feel free to provide feedback as deemed necessary.

Thanks