nano_RF wrote on Aug 24th, 2008, 7:54pm:I am not sure what you mean by that LDO can work in triode mode (you are inferring that it will not work similarly for miller compensation on pass device).
Hi,
Sorry I was not clear but actually I meant the pass transistor entering in triode region as you correctly inferred.
Under such condition the loop gain will be smaller and therefore stability will be relaxed.
The main problem is when the pass transistor is under saturation mode, and specially for very large pass transistors driving large load currents as you pointed out. The reason for this is the large VGS associated to this device pushing this (usually relative high frequency) pole down to the dominant pole range.
Bottom line, increasing the error amplifier gain most probably will play against stability.
Berti: I totally agree with you if the design relies on the dominant pole being set by such stage and I doubt something (easy) can be done about it
Regards
Tosei