The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 22nd, 2024, 11:18am
Pages: 1 2 
Send Topic Print
Intergrator Chopping Problem (Read 11725 times)
frank007
Junior Member
**
Offline



Posts: 13

Intergrator Chopping Problem
Sep 06th, 2008, 2:56pm
 
I am working on the first integrator in the DT delta-sigma modulator. I am using chopper stabilization. I have made the INV control signal non-overlapping and advance-open the SW connected to virtual ground.

The integrator works well when chopping is disabled (and OTA is at transistor level). Also it works well when chopping is enabled and the OTA used is ideal.

However, when the chopping is enabled and the OTA is real, the result deteriorates. Am I doing the chopping in a right way? Thanks.


Back to top
 
 
View Profile   IP Logged
HdrChopper
Community Fellow
*****
Offline



Posts: 493

Re: Intergrator Chopping Problem
Reply #1 - Sep 7th, 2008, 5:41pm
 
Hi Frank,

It would be good if you could describe how your circuit degrades when you have the chopper active with the actual OTA circuit.
The switches connection seem to be ok concerning the chopper phases. If you say the chopper works well with an ideal OTA I would imagine you might be running into slew rate or bandwidth problems when you use the actual OTA: I imagine you might have some BW limitation at the output of your OTA due to the large output impedance. If this BW is not much larger than the chopping freq then you are in trouble. Also it is usually recommended for SC amplifiers to run the chopper at exactly half of the switched cap clock frequency.

Regards
Tosei
Back to top
 
 

Keep it simple
View Profile   IP Logged
frank007
Junior Member
**
Offline



Posts: 13

Re: Intergrator Chopping Problem
Reply #2 - Sep 8th, 2008, 9:04am
 
Thanks for your reply. Actually I am doing an incremental ADC, which means my input is a DC signal and the output is a conversion result given by the decimation filter. And I measure the error between the input and the conversion result.

This error increases when I am using real OTA and chopping. It is ok for real OTA and no-chooping, and also ok for ideal OTA and chopping.

Yesterday I have tried to put an ideal gain boosting to the real OTA, increasing the OTA gain from 40 dB to 60 dB. It seems that the circuit now works for both real OTA and chopping.

My explanation is that since there is a voltage difference between the OTA virtual ground and there is input cap there, when chopping is used, it is like this small voltage difference is put into the integrator with alternative polarity, thus mess up the result. If OTA gain is increased, this voltage difference get reduced, and its effect reduce as well. I don't whether it is right or not.

Back to top
 
 
View Profile   IP Logged
Tlaloc
Community Member
***
Offline



Posts: 81
Dallas, TX
Re: Intergrator Chopping Problem
Reply #3 - Sep 8th, 2008, 1:37pm
 
Have you run some sims with a large input signal?  DC is fine, but you really want to verify that the amp can handle the slewing from a large input.  I am assuming that your ideal OTA is some finite gain element with a possible pole to look at finite bandwidth, but I am pretty sure that you have not put in any slew limiter in your model.  When you added the additional gain boosting, did you break it in a way that it would give ideal slewing?

Back to top
 
 
View Profile   IP Logged
HdrChopper
Community Fellow
*****
Offline



Posts: 493

Re: Intergrator Chopping Problem
Reply #4 - Sep 8th, 2008, 8:34pm
 
frank007 wrote on Sep 8th, 2008, 9:04am:
My explanation is that since there is a voltage difference between the OTA virtual ground and there is input cap there, when chopping is used, it is like this small voltage difference is put into the integrator with alternative polarity, thus mess up the result. If OTA gain is increased, this voltage difference get reduced, and its effect reduce as well. I don't whether it is right or not.




I'm not sure I'm getting the idea behind your explanation. You are chopping the amplifier, that is because it has some input referred offset which - if the OTA is properly designed - should be mostly generated by the input diff pair. So having an input offset at the OTA virtual ground terminals is to be expected, but that should not affect the way the chopper works while using an ideal or actual OTA.

Certainly having a low loop gain (40dB) will have some effect on chopper efficiency since bandwidth limitations of your OTA will show up as gain reduction for the chopper. As you increase the loop gain this effect will be more and more negligible up to the point that you will not notice such gain reduction in the loop gain provided such gain is large enough.

I'm more inclined to think this is what might be going on (or some slew rate limitation as I and Tlaloc suggested) provided I do not know exactly if the degradation shows up as a gain reduction, distorted signal or anything else.

Regards
Tosei
Back to top
 
 

Keep it simple
View Profile   IP Logged
frank007
Junior Member
**
Offline



Posts: 13

Re: Intergrator Chopping Problem
Reply #5 - Sep 9th, 2008, 3:41pm
 
There is no slewing limiter in ideal OTA. What puzzles me is that the modulator works with real OTA and no-chopping. So the OTA slewing should meet the requirement. And supposedly chopping should not increase the slewing requirement.

Back to top
 
 
View Profile   IP Logged
frank007
Junior Member
**
Offline



Posts: 13

Re: Intergrator Chopping Problem
Reply #6 - Sep 9th, 2008, 3:58pm
 
I think the input refered offset is a DC signal (or 1/f noise), and after chopping, it is moved out of the signal band. But the small voltage difference at the input of the OTA is a noise-shaped signal (since it is 1/A of the integrator 1 output voltage. So the chopping of this signal will probably move the quantization noise back into the signal band.

I guess the choping supposedly will not increase the OTA requirement. I am not getting "bandwidth limitations of your OTA will show up as gain reduction for the chopper". Could you explain that? Thanks.

Back to top
 
 
View Profile   IP Logged
Tlaloc
Community Member
***
Offline



Posts: 81
Dallas, TX
Re: Intergrator Chopping Problem
Reply #7 - Sep 9th, 2008, 8:48pm
 
First off, the major drawback of chopping is a greatly increased slewing requirement.  Let's assume that your capacitor gain in your integrator without chopping is 1/4.  For every full scale (FS) worth of input signal, you output is 1/4*FS.  So, without chopping, if your input is FS and your output is 3/4*FS, you output would still only need to step by 1/4*FS (with ideal rail-to-rail outputs) to bring the output to +FS.  With chopping enabled, you would need to drive the output from 3/4*FS to -FS, which is a huge difference in output step.  Since most OTA's enter a slewing condition during these large transients, chopping exacts a huge slewing burden.  As an aside, continuous time chopping exacts a huge bandwidth burden.

Quote:
I am not getting "bandwidth limitations of your OTA will show up as gain reduction for the chopper".

If your OTA does not settle properly, either through bandwidth limitations or slewing limitations, that shows up as a gain reduction.  This is simply due to the fact that the charge on your caps are not what you expect them to be.  There would always be less charge, so therefore it would be indistinguishable from an integrator with lower gain.

Quote:
So the chopping of this signal will probably move the quantization noise back into the signal band.

I don't know why you say that the error voltage on the summing junctions would be a noise-shaped signal, though.  The very-low frequency errors--i.e. offset, 1/f noise, cap mismatch, and some charge injection--would be up-converted to the chopping frequency.  However, this is not a noise signal.  It can be explicitly defined by the charge equations, and hence, I would not agree that it would move the quantization noise into the signal band.
Back to top
 
 
View Profile   IP Logged
frank007
Junior Member
**
Offline



Posts: 13

Re: Intergrator Chopping Problem
Reply #8 - Sep 10th, 2008, 3:35pm
 
Tlaloc wrote on Sep 9th, 2008, 8:48pm:
First off, the major drawback of chopping is a greatly increased slewing requirement.  Let's assume that your capacitor gain in your integrator without chopping is 1/4.  For every full scale (FS) worth of input signal, you output is 1/4*FS.  So, without chopping, if your input is FS and your output is 3/4*FS, you output would still only need to step by 1/4*FS (with ideal rail-to-rail outputs) to bring the output to +FS.  With chopping enabled, you would need to drive the output from 3/4*FS to -FS, which is a huge difference in output step.  Since most OTA's enter a slewing condition during these large transients, chopping exacts a huge slewing burden.  As an aside, continuous time chopping exacts a huge bandwidth burden.


I am just flip-flop the OTA in the integrator, so the integrator output should be exactly the same as the case without chopping. Why is there the difference of the output step.

Quote:
If your OTA does not settle properly, either through bandwidth limitations or slewing limitations, that shows up as a gain reduction.  This is simply due to the fact that the charge on your caps are not what you expect them to be.  There would always be less charge, so therefore it would be indistinguishable from an integrator with lower gain.


OK。 I think that's right.

Quote:
I don't know why you say that the error voltage on the summing junctions would be a noise-shaped signal, though.  The very-low frequency errors--i.e. offset, 1/f noise, cap mismatch, and some charge injection--would be up-converted to the chopping frequency.  However, this is not a noise signal.  It can be explicitly defined by the charge equations, and hence, I would not agree that it would move the quantization noise into the signal band.


I think the output of integrator 1 is noise shaped ((1-z^-1)^3*(z^-1/(1-z^-1))). The voltage at the OTA virtual ground is just 1/A of the OTA output, thus is noise-shaped as well. If it is chopped, it will be moved by fs/2, and mess up the signal band. Hope that clarify what I want to say.
Back to top
 
 
View Profile   IP Logged
Tlaloc
Community Member
***
Offline



Posts: 81
Dallas, TX
Re: Intergrator Chopping Problem
Reply #9 - Sep 10th, 2008, 6:37pm
 
I was thinking that you were chopping before the input caps, but I realize that is not the case.  As far as the slewing requirement, then, it depends on your amp architecture.  If you have a two stage with a Miller cap, you still have to slew that cap.

Quote:
If it is chopped, it will be moved by fs/2, and mess up the signal band.

Is this a bandpass Delta-Sigma?

Quote:
I think the output of integrator 1 is noise shaped

Remember that with Delta-Sigma's, there are two transfer functions, the signal TF and the noise TF.  It depends on your exact architecture, but there are some that treat the noise at the input to the first integrator as a signal.  The real question here is what is the transfer function for any input--noise, offset, charge injection, etc.-- at the input to the integrator.  At the output, all error sources and the signal are indistinguishable.

Quote:
So the chopping of this signal will probably move the quantization noise back into the signal band.

This was the confusing sentence to me.  The quantization noise should be unaffected by any of this.  Other noise sources may be shifted into the signal band, though.
Back to top
 
 
View Profile   IP Logged
HdrChopper
Community Fellow
*****
Offline



Posts: 493

Re: Intergrator Chopping Problem
Reply #10 - Sep 11th, 2008, 8:00pm
 
frank007 wrote on Sep 10th, 2008, 3:35pm:
I think the output of integrator 1 is noise shaped ((1-z^-1)^3*(z^-1/(1-z^-1))). The voltage at the OTA virtual ground is just 1/A of the OTA output, thus is noise-shaped as well. If it is chopped, it will be moved by fs/2, and mess up the signal band. Hope that clarify what I want to say.


If all the voltage at the OTA virtual ground were noise-shaped, so the input signal should be. This should not be the case for DS modulator where only the quantization noise gets shaped. Actually only the noise generated at the input of the loop comparator gets shaped while the input signal (where OTA offset and 1/f can be included too) does not.

In other words I think both offset and 1/f noise at the input of the OTA are only affected by the signal transfer function and not by the noise transfer function...

From this I still believe you have a slew rate/ BW limitation here...

Tosei
Back to top
 
 

Keep it simple
View Profile   IP Logged
frank007
Junior Member
**
Offline



Posts: 13

Re: Intergrator Chopping Problem
Reply #11 - Sep 13th, 2008, 4:58pm
 

Quote:
Is this a bandpass Delta-Sigma?


no it is not.

Quote:
This was the confusing sentence to me.  The quantization noise should be unaffected by any of this.  Other noise sources may be shifted into the signal band, though.


Well, if the input cap of the first integrator is not considered and chopping is not used, I agree.
Back to top
 
 
View Profile   IP Logged
frank007
Junior Member
**
Offline



Posts: 13

Re: Intergrator Chopping Problem
Reply #12 - Sep 13th, 2008, 5:12pm
 
Quote:
If all the voltage at the OTA virtual ground were noise-shaped, so the input signal should be.

Tosei


Thanks for the reply.

I think for the low-distortion structure, the input signal is canceled at the input adder. Thus only the noise-shaped quantization noise goes through the first integrator. Suppose the noise-shaping is 3rd order, the 1st INT output is a 2nd order noise-shaped quantization noise.

Since the virtual ground voltage is simply 1/A of the INT1 output (where A is the DC gain of the OTA), the virtual ground voltage consists of a 2nd order noise-shaped quantization noise (divided by A).

Suppose there is input cap at the OTA virtual ground, the virtual ground voltage will be stored there. If chopping is not used, this charge will probably just change the integrator gain. If chopping is performed at fs/2, the virtual ground charge will be modulated at fs/2 and injected to the integrator cap.

That is my understanding.
Back to top
 
 
View Profile   IP Logged
Tlaloc
Community Member
***
Offline



Posts: 81
Dallas, TX
Re: Intergrator Chopping Problem
Reply #13 - Sep 15th, 2008, 7:45pm
 
Quote:
Since the virtual ground voltage is simply 1/A of the INT1 output (where A is the DC gain of the OTA), the virtual ground voltage consists of a 2nd order noise-shaped quantization noise (divided by A).

I do agree that there will be an error term on the summing junctions due to this.  Also, there will be shifting of noise in the frequency domain, but low freq noise would get shifted up while nyquist freq noise would get shifted down.  The noise would be filtered by the integrator transfer function, and the swap would take place again.  This is a better scenario since flicker noise is removed by the chopping and shaped by the integrator.  Do have some reason to believe that this would ultimately cause more noise in the signal band?  
Back to top
 
 
View Profile   IP Logged
frank007
Junior Member
**
Offline



Posts: 13

Re: Intergrator Chopping Problem
Reply #14 - Sep 16th, 2008, 8:36am
 
Quote:
Do have some reason to believe that this would ultimately cause more noise in the signal band?  


I guess increasing A will reduce this error. In my case, looks 60 dB works but 40 dB doesn't.
Back to top
 
 
View Profile   IP Logged
Pages: 1 2 
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.