hi guys, i am now designing a LNA with specs of 0dBm input P1dB, 18dB power gain, and 1.5dB noise figure of 1710~1980 MHz.
   I have several questions:
   1. Is the LNA's behavior more like PA, 30 parallel bipolars to provide 60mA current. Should i take some simulation like PA to ensure its performance.
   2. Is 0dBm input power level possible for SiGe HBTs, tran and pss+pac simulation results show the spec can be met, but i wonder whether the HBT can stand the input power level?
   3. Would Darlington Structure show some advantage  over simple common-emitter structure, Since at higher frequency, the parasitic inductance connected to bipolar emitter degrade the LNA's power gain dramatically.
   i do appreciate if someone can help me!!!

First thank you for your advice. i have already tried simple common-emitter and cascode topology before. In fact, i do not think these specs are easy to met after simulation. for the cascode amp, the simulation results showed it's hard to achieve such a high linearity. For higher frequency such as 1710MHz, the emitter degeneration inductance would influence the Gmsg(Maximux power gain that can be achieved while the amp is stable) with a current of 50~60mA, in my design the relationship is
LE           Gmsn
0.1nH      19.5dB
0.2nH      16.6dB
0.3nH      14.5dB
Some process may provide special ground metal panel beneath the substrate to minimize the bondwire inductance. Yet the process i am using does not provide this step, it's diffcult to control the bondwire inductance to such a low value. This is why i wonder is there any special circuit topology to meet the gain spec.
Anyway, thanks for your help!

a 0dBm input P1dB requires such a large current as i have mentioned. Besides, certainly only one transistor cannot stand such a current, so quite a number of transistors are in parallel to allow the current.