Hi all,

I am new to mixed simulation.

I have a behavoral model(in verilog) of an FSM and i want to give this output to a anlog input.

1. can i give input to the FSM like CLK, En, Reset signal from vsource (analogLib) ?

I have connected a L2E module for each FSM output to the each analog input. Hope this is right?

I am doing simulation in AMS-Environment and got some error.
---------------------------------------------------------------------------
ncelab: *E,CUVNCM (/design/ADC/schematic/verilog.vams,86|33): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance ADC_test.I1.I246.
vinclk ), .gnd( cds_globals.\gnd!  ), .vdd( cds_globals.\vdd!  ), .Aout(
                                                            |
ncelab: *E,CUVNCM (/designs/ADC/schematic/verilog.vams,86|61): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance ADC_test.I1.I246.
vdif ), .Ain( vin ) );
----------------------------------------------------------------

Thanks

Dinac,

 Is connectLib included in your libraries? The connection modules
are in this library and it needs to be specified in your cds.lib file.
Also, the connect module insertion is automatic, can you explain
how you connected two modules with an L2E?

                                                           Best Regards,

                                                               Sheldon