dinac
New Member
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Posts: 6
Belgium
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Hi all,
I am new to mixed simulation.
I have a behavoral model(in verilog) of an FSM and i want to give this output to a anlog input.
1. can i give input to the FSM like CLK, En, Reset signal from vsource (analogLib) ?
I have connected a L2E module for each FSM output to the each analog input. Hope this is right?
I am doing simulation in AMS-Environment and got some error. --------------------------------------------------------------------------- ncelab: *E,CUVNCM (/design/ADC/schematic/verilog.vams,86|33): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance ADC_test.I1.I246. vinclk ), .gnd( cds_globals.\gnd! ), .vdd( cds_globals.\vdd! ), .Aout( | ncelab: *E,CUVNCM (/designs/ADC/schematic/verilog.vams,86|61): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance ADC_test.I1.I246. vdif ), .Ain( vin ) ); ----------------------------------------------------------------
Thanks
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