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MASH（2-1 cascade)Delta-Sigma AD design question
Sep 24^th, 2008, 1:04am

Hi. guys,

I want to design a third-order delta-sigma adc and I want to try MASH(multi-stage noise shaping) structure with 2-1 cascade. The behavioral model is shown below.

I have question about the noise cancellation logic. How do I realize the gain block "1/c1" and "b1-1" . I think the two quantizer outputs y1 and y2 are signle-bit data, what it will be like when they pass the "1/c1" and "b1-1" ?

The D block is simply realized by a D-Flipflop ("1/z"), while XOR gate can be used to realize ("1-1/z").

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MASH2-1_cascade.JPG

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Berti

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Re: MASH（2-1 cascade)Delta-Sigma AD design question
Reply #1 - Sep 24^th, 2008, 3:50am

Hi,

First of all you should make sure that 1/c1 and b1-1 are "good" numbers. Written as a fractional number N/D, N should be an integer, and D should be [1,2, 4, 8, 16 etc.]. Otherwise the digital implementation becomes nasty. Then I recommend to use a proper digital design flow (VHDL/Verilog,Synthesis) rather than hand-crafted digital design. I guess that the synthesis-tool is much better in logic optimization than you can do by hand.

Cheers

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skythunder

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Re: MASH（2-1 cascade)Delta-Sigma AD design question
Reply #2 - Sep 24^th, 2008, 6:54pm

Berti wrote on Sep 24^th, 2008, 3:50am:

Hi,

First of all you should make sure that 1/c1 and b1-1 are "good" numbers. Written as a fractional number N/D, N should be an integer, and D should be [1,2, 4, 8, 16 etc.]. Otherwise the digital implementation becomes nasty. Then I recommend to use a proper digital design flow (VHDL/Verilog,Synthesis) rather than hand-crafted digital design. I guess that the synthesis-tool is much better in logic optimization than you can do by hand.

Cheers

Thanks for the reply, Berti !
But the point that confused me is : if y1, y2 are single-bit data, and the result y is also single bit, does those gain block 1/c1, b1-1 make any sense ? For example, if C1=0.25, so 1/c1 = 4 (integer), what it will be like when a one-bit data times 4 ? Does it make sense?
I hope I may misunderstand this noise cancellation logic, but I can't find answer yet .

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Berti Community Fellow Offline Posts: 356	Re: MASH（2-1 cascade)Delta-Sigma AD design question Reply #3 - Sep 24^th, 2008, 10:30pm I think that you single bit output needs to be decoded like this 0 -> -1 1 -> 1 Multiplying by 4 therefore gives -4 and 4. Expressed in 2's complement: 0100 and 1100. Cheers
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ethan Community Member Offline Posts: 36	Re: MASH（2-1 cascade)Delta-Sigma AD design question Reply #4 - Aug 17^th, 2013, 10:37pm Hi everybody, sorry to bring this long old topic up again. according to Berti, if 1/c1=0100 (2's complement) and b1_1 = 1100, then that error cancellation circuit should have 4bit bus. Then the first XOR gate (right after 1/c1 and b1_1) should have two 4-inpputs? Is that right? thx.
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