Berti wrote on Sep 24th, 2008, 3:50am:Hi,
First of all you should make sure that 1/c1 and b1-1 are "good" numbers. Written as a fractional number N/D, N should be an integer, and D should be [1,2, 4, 8, 16 etc.]. Otherwise the digital implementation becomes nasty. Then I recommend to use a proper digital design flow (VHDL/Verilog,Synthesis) rather than hand-crafted digital design. I guess that the synthesis-tool is much better in logic optimization than you can do by hand.
Cheers
Thanks for the reply, Berti !
But the point that confused me is : if y1, y2 are single-bit data, and the result y is also single bit, does those gain block 1/c1, b1-1 make any sense ? For example, if C1=0.25, so 1/c1 = 4 (integer), what it will be like when a one-bit data times 4 ? Does it make sense?
I hope I may misunderstand this noise cancellation logic, but I can't find answer yet .