In your modified version, are "vout" and "VOUT" distinct?  Verilog-A is case-sensitive, but I'm not sure whether you were careful when excerpting your model.

I'd add two new nodes:
 electrical int_iout, int_vout;
and contribute both like this:
 I(int_iout) <+ V(int_iout) + transition( 0.0, rdelay);
 I(int_vout) <+ V(int_vout) + transition( 0.0, fdelay);
then
 if (comp_flag == 1)
   I(VOUT, GND) <+ V(int_iout);
 else
   V(VOUT, GND) <+ V(int_vout);

The internal nodes have 1-Ohm resistors on them that convert the current into a voltage; there are funny tricks when you both contribute and probe I(iout) as in your code.  In mine, the probe is always V(x).

Oh, and I assume the "0.0" first arg of transition() is just a dummy, you actually have something that changes there.