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godfather Community Member Offline Posts: 36	Critical Question Sep 26^th, 2008, 1:26pm Hello all, This is struggling in my mind, whats the difference between verilog, verilog-A,verilog-ams,vhdl,and vhdl-ams.
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Geoffrey_Coram

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Posts: 1999
Massachusetts, USA

Re: Critical Question
Reply #1 - Sep 29^th, 2008, 4:58am

Verilog was IEEE standard 1364. It has now been subsumed by IEEE std 1800, SystemVerilog. Verilog is a hardware description language -- essentially a programming way to describe an electronic circuit you are trying to design/build/simulate.

Verilog-A was an analog behavioral language syntactically based on Verilog; it was subsumed (made an official subset) of Verilog-AMS, which is an Accellera standard. (Accellera plans to donate this to the IEEE at some point.)

VHDL (IEEE std 1076) and VHDL-AMS (1076.1) are a "rival" hardware description language and its analog and mixed-signal extensions.

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If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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godfather Community Member Offline Posts: 36	Re: Critical Question Reply #2 - Sep 29^th, 2008, 12:25pm thnks for the reply. one quick question so can you build a ripple carry adder in verilog ams and if so then whats the difference between that building in system verilog and verilog ams.
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Critical Question Reply #3 - Sep 30^th, 2008, 1:53pm You can build the adder in Verilog, and both SV and V-AMS are supersets of Verilog, so you can do it in either, and there should be no difference.
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jbdavid

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Posts: 378
Silicon Valley

Re: Critical Question
Reply #4 - Oct 4^th, 2008, 12:22am

This has probable been stated here - and other places - several times.. did you try to search for an answer first?

Verilog started as a language to describe and verify LOGIC - iow DIGITAL.

Verilog-A is a similar language to describe ELECTRICAL/Conservative systems that can be represented as Lumped Element models.. (R, L, C, transistors etc.. this supports some other physical domains including MAGNETIC, and Positional, which make it very useful to model things that need to work with logic like amplifiers and MEMS accelerometers. Verilog-A as a subset is becoming the primary language to define "compact models" of devices (think BJT, MOS3 or BSIM4) allowing a single definition to be compiled into many simulators including GNUCAP, Spectre, and Hspice..

Verilog-AMS is a superset of Verilog and Verilog-A, also adding some features to support automating the connections between logic and electrical, as well as allowing full interaction between electrical things and digital things

VHDL is a hardware description language that supports many sorts of system level design, including both logic and some analog systems.. but did NOT have any support for solving analog dynamic systems (ie in terms of derivatives or integrals.. ) on the other hand real numbers have been well supported, even allowing one to define a wire that carries a "record" containing several real numbers.

VHDL-AMS added dynamics support to VHDL, but there is no VHDL-A subset. thus leaving it unsuitable for compact modeling.

SystemVerilog adds some system level constructs to Verilog, (ie real numbers, and "structures" ) as well as an assertion language to support digital verification. -- oops sorry you didn't ask about that did you.

Its a complicated world.. good luck.
jbd

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jbdavid
Mixed Signal Design Verification

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godfather Community Member Offline Posts: 36	Re: Critical Question Reply #5 - Oct 8^th, 2008, 10:15pm thnks all for amazing replies.......... but the real thing is to design in mixed signal.... ::)
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