jbdavid
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This has probable been stated here - and other places - several times.. did you try to search for an answer first?
Verilog started as a language to describe and verify LOGIC - iow DIGITAL.
Verilog-A is a similar language to describe ELECTRICAL/Conservative systems that can be represented as Lumped Element models.. (R, L, C, transistors etc.. this supports some other physical domains including MAGNETIC, and Positional, which make it very useful to model things that need to work with logic like amplifiers and MEMS accelerometers. Verilog-A as a subset is becoming the primary language to define "compact models" of devices (think BJT, MOS3 or BSIM4) allowing a single definition to be compiled into many simulators including GNUCAP, Spectre, and Hspice..
Verilog-AMS is a superset of Verilog and Verilog-A, also adding some features to support automating the connections between logic and electrical, as well as allowing full interaction between electrical things and digital things
VHDL is a hardware description language that supports many sorts of system level design, including both logic and some analog systems.. but did NOT have any support for solving analog dynamic systems (ie in terms of derivatives or integrals.. ) on the other hand real numbers have been well supported, even allowing one to define a wire that carries a "record" containing several real numbers.
VHDL-AMS added dynamics support to VHDL, but there is no VHDL-A subset. thus leaving it unsuitable for compact modeling.
SystemVerilog adds some system level constructs to Verilog, (ie real numbers, and "structures" ) as well as an assertion language to support digital verification. -- oops sorry you didn't ask about that did you.
Its a complicated world.. good luck. jbd
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