An excellent response. Let me add a few points of my own. I have not made many charge pumps, but a few, and all with some sort of regulation loop.
I used the following approach:
1. Build a simplified model of the charge pump, replacing transistors with ideal switches (finite Ron/Roff), caps, and adding dominant parasitic caps.
2. Run a PSS+PAC analysis on the charge pump to get the transfer function of each stage.
3. Find the most important poles and zeros by "eyeballing" the AC response (gain and phase).
4. Usually, there is always 1 pole which is dominant, the one at the output in most cases, and this is much smaller than the clock frequency => granularity effects can be neglected, and a simplified LTI analysis can be done.
5. In order to check that the model is really valid, I then run a transient analysis of the simplified and the real charge pumps, and look at their step responses (change the input a bit), and compare this to the step response resulting from the LTI model (You need to scale the voltage levels accordingly). I usually got an excellent fit.
6. Based on this, I design a regulator which keeps the loop stable. Since the system dominant pole is usually quite low, it is fairly simple to build a relatively low gain regulator with a pole at a much higher frequency. Stability is best checked using the root locus. And yes, the dividers I used always relied on lead-lag compensation to prevent that pole becoming critical.
For me, the whole process above took a couple of days to do, and was worth the effort. The loop worked fine even on silicon.
Tlaloc: How do you work out a z-domain model for the stages? I always find it painful to do this, largely because charge pump stages are neither unidirectional, nor lossless, and the charge transferred from stage to stage is a function of the output load -> TF of stage n depends on load seen at all stages n+1, n+2, etc.
Regards,
Vivek
Tlaloc wrote on Sep 30th, 2008, 8:22pm:First off, I am not familiar with the topology that you are talking about. I might have seen it before, but I don't know the name. I have spent a lot of time with Dickson charge pumps and level-shifting variations for the most part to use for E2 and flash. With that disclosure, I'll share some of the things that I have learned.
The vast majority of the designers that I have seen design charge pumps want to model it as a single pole system, which, unless it is a single stage, is not the case. If you go through the charge equations, you can come up with the z-domain transfer function. For an even number of pumping capacitors, you get an equal number of poles and zeros. Assuming that you model the z-domain transfer function as a continuous time s-domain function, the frequency response is close to a lag-lead compensator as the poles and zeros stick close to each other.
The best way to stabilize such a system is with a lead-lag compensator. This is quite frequently easy to do since most of these charge pumps have a resistive divider for the feedback. If you place a capacitor in parallel with the upper capacitor in the feedback, you create a passive lead-lag network. Since the network is passive, the maximum zero-pole separation that you can create is one decade. This can be troublesome depending on the exact nature of your charge pump since the pole-zero distance of the charge pump can be larger than that. I typically see something like two decades.
In short, with many types of circuits, if you have some slight problems with stability in resistive feedback networks, a capacitor in parallel with the top resistor can help. I have seen a few charge pump design use this solution without any analysis.
As far as references, I don't really know of any. Sorry.