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[Q] Verilog-A Modeling (Read 1826 times)

kidhyun

Junior Member

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Posts: 14

[Q] Verilog-A Modeling
Oct 06^th, 2008, 5:25pm

Hi,

� �In a test bench for circuit, I added Verilog-A block which does only

> � parameter real offset = 0;
> � analog
> V(out) <+ V(in) + offset;

� �,where the offset is by default set to 0 in my simulation.
� �(I inserted this block in some place in the circuit)

� �I assumed that this block would not make any difference in the simulation result.

� �But when I checked the spectrum (using psd) there was significant difference between results with and without this block.

� �Just the existence of this block affect the time step in solving the node equations?

Thank You

�

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jbdavid

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Posts: 378
Silicon Valley

Re: [Q] Verilog-A Modeling
Reply #1 - Oct 6^th, 2008, 9:37pm

I'm going to go out on a limb here, and GUESS that by
"without" this circuit, you just had a wire ?

which would mean that you would have had a voltage, and, as needed current along that wire..

with this module you have, effectively an ideal VCVS with the control voltage being the input + offset..
Quite a different thing than

V(in,out) <+ offset;

which defines a branch between in, and out, with a fixed voltage (maybe 0) leaving its current unconstrained.. which will behave MUCH more like a wire..

HTH.

jbdavid
Mixed Signal Design Verification

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kidhyun Junior Member Offline Posts: 14	Re: [Q] Verilog-A Modeling Reply #2 - Oct 6^th, 2008, 11:51pm Thank you. I think I made a mistake there. It works fine now.
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