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Jacobian error in Cadence veriloga simulation (Read 2687 times)
gandhi_gaurav
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Jacobian error in Cadence veriloga simulation
Oct 08th, 2008, 3:29am
 

I am trying to run a simple simulation to calculate the amount of charge that passes through a simple device and am getting a "jacobian" error.

The code that I am using is very simple as follows:


`include "constants.vams"
`include "disciplines.vams"

module res1(out,in);
inout out,in;
electrical out,in;
real i,charge,finalcur;

analog begin
i= I(out,in);
charge = idt(i);
finalcur = ddt(charge);
end
endmodule


The stimulus is a simple voltage source with 1mOhm resistance connected in series to voltage source. This is then applied to the veriloga block I have designed.

and the error that I am getting is zero found in diagonal of Jacobian.

Any guesses what am I doing wrong ?
How can I calculate the amount of charge that is passing through a device ?
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Ken Kundert
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Re: Jacobian error in Cadence veriloga simulation
Reply #1 - Oct 9th, 2008, 3:53pm
 
You need to specify an initial condition for the idt operator.

-Ken
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gandhi_gaurav
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Re: Jacobian error in Cadence veriloga simulation
Reply #2 - Oct 31st, 2008, 3:40am
 
Perfect !!

It works !!
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