Hi everyone:

I created a 5-bit adder in Verilog-A, and when I tried to instantiate the 5-bit adder, FA_5bit, in a larger verilog-A system, I run into the following problem:
FA_5bit i2 (.A(IN[2:0]), .B({ J, K, H }), .CO(CO), .S(S[2:0]), .CI(CI)); HSPICE complains about the concatenation symble "{" saying "syntax error"
The simulation would otherwise go through I change the code as the following:
FA_5bit i2 (.A(IN_SUB[2:0]), .B(IN_SUB[2:0]), .CO(CO), .S(S[2:0]), CI(CI));

Could someone points me where I was wrong?

Many thanks
Erik

Thanks Patrick.

So before the new release, is there any work around? Or I have to split the 3-bit FA into single bit adder adder and connect them together?

Thanks