Hi all:
I have a question regarding getting access to hierarchical node in VA and hope it can be answered by experts in this forum. For example, I need to get access to two nodes called global.vdd and global.vss. In Verilog-HDL, I simply create a module called global and their net can be hierarchically referred. I tried the similar thing in verilog-A, but it seems to fail.
One example would be that if I need to instantiate the following VA model
     module test(A, Z);
           input A;
           output Z;
           electrical A;
           electrical Z;

           electrical B;

           test1 i0 (.A(B), .Z(B));
           test2 i1 (.A(B),.B(global.vss), .Z(Z));
     endmodule

I tried to write a separate global.va model which is having vss, and include the file in my hspice input file, but no luck.

Your opinion will be highly appreciated!