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icsoul

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About mix simulation for verilog-a and HSPICE
Oct 09^th, 2008, 9:46pm

When I simulated HSPICE netlist, the simulation result is correct.

Then I added a verilog-a module to simulate with the HSPICE netlist, the result is not correct. But the va module added is just used to test the HSPICE netlist result and not affect the function of HSPICE netlist at all.

Why this happened?

The algorithm has conflict?

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patrick Junior Member Offline Posts: 30 Santa Rosa, CA.	Re: About mix simulation for verilog-a and HSPICE Reply #1 - Oct 10^th, 2008, 7:59am Assuming the additional VA module does not change the electrical network nor has any $boundstep calls then the addition of this module should not change anything. If you post the module and netlist we should be able to provide an answer. Patrick
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icsoul Junior Member Offline Posts: 29	Re: About mix simulation for verilog-a and HSPICE Reply #2 - Oct 13^th, 2008, 4:03am I also think it will not change anything. But it do changed the simulation result. Is it the HSPICE bug? I simulated it with version 200606. The netlist is private, so it can't be upload here,sorry.
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patrick

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Re: About mix simulation for verilog-a and HSPICE
Reply #3 - Oct 13^th, 2008, 10:07am

It's hard to help without the netlist or VA file. Try making the VA module really simple - use no ports and just do a strobe like this:

module test_me();
analog $strobe("Got here");
endmodule

then instantiate in the netlist as:

x1 test_me

Do the results change now? If not add more statements to the analog block to make it look more like the module that's causing trouble.

Patrick

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icsoul Junior Member Offline Posts: 29	Re: About mix simulation for verilog-a and HSPICE Reply #4 - Oct 14^th, 2008, 2:36am I just included the va module with .hdl and didn't use it. Even this, the simulation results are also different. So I think it may be the bug of HSPICE.
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: About mix simulation for verilog-a and HSPICE Reply #5 - Oct 14^th, 2008, 6:26am What's in your va file? I remember something about some simulators letting you replace subckts or even built-in models with Verilog-A. Try changing the name of your module to something really strange that you're sure doesn't exist in your circuit.
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patrick

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Re: About mix simulation for verilog-a and HSPICE
Reply #6 - Oct 14^th, 2008, 7:27am

By default, in HSPICE, even if a loaded VA module has the same name as a sub-circuit it will not override that sub-circuit definition. Resolution goes as:

Given an x instance say,

x1 test_me

Then the system will use the following resolution:

- is test_me a sub-circuit definition?
- is it a model card referencing a VA module?
- is it a paramset or module?
- none of the above => error

Patrick

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Tlaloc

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Re: About mix simulation for verilog-a and HSPICE
Reply #7 - Oct 14^th, 2008, 9:29pm

I personally have seen non-convergence using HSPICE testbenches that are written in verilog-a. In this case, I know that there are no name conflicts, nor was I doing anything "crazy", i.e. I was just trying to replace pwl voltage sources. This did not give reliable results, so I went back to my standard PWL's. I know that this is not an answer that anyone hopes for, but my experience with HSPICE was to assume that the simulator (while using verilog-a) was screwing something up.

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patrick Junior Member Offline Posts: 30 Santa Rosa, CA.	Re: About mix simulation for verilog-a and HSPICE Reply #8 - Oct 14^th, 2008, 9:38pm If you can post the netlist and VA pwl that's not working I'm happy to take a look. Patrick
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: About mix simulation for verilog-a and HSPICE Reply #9 - Oct 15^th, 2008, 5:25am Did you use $bound_step and $discontinuity ? I still don't understand what could go wrong in icsoul's scenario where he just had the .hdl statement and no instance of the object ...
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icsoul

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Re: About mix simulation for verilog-a and HSPICE
Reply #10 - Oct 15^th, 2008, 7:15pm

Geoffrey_Coram wrote on Oct 14^th, 2008, 6:26am:

What's in your va file?

I remember something about some simulators letting you replace subckts or even built-in models with Verilog-A. �Try changing the name of your module to something really strange that you're sure doesn't exist in your circuit.

I don't think the reason is your point.
Because I included one va module had a different name with the circuit.

It seems that the Gate Currents are changed when a va module is included.

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icsoul

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Re: About mix simulation for verilog-a and HSPICE
Reply #11 - Oct 15^th, 2008, 7:29pm

Tlaloc wrote on Oct 14^th, 2008, 9:29pm:

I personally have seen non-convergence using HSPICE testbenches that are written in verilog-a. �In this case, I know that there are no name conflicts, nor was I doing anything "crazy", i.e. I was just trying to replace pwl voltage sources. �This did not give reliable results, so I went back to my standard PWL's. �I know that this is not an answer that anyone hopes for, but my experience with HSPICE was to assume that the simulator (while using verilog-a) was screwing something up.

I agree with you,Tlaloc.
The problems I meet are:
1. When I simulated pure circuits, I got one result;
2. When I simulated circuits that just included the va module but not used, I got second result;
3. When I simulated circuits includesd va module and used it, I got another result.

I mean I got three different results in the three conditions.

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icsoul

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Re: About mix simulation for verilog-a and HSPICE
Reply #12 - Oct 15^th, 2008, 7:39pm

patrick wrote on Oct 14^th, 2008, 9:38pm:

If you can post the netlist and VA pwl that's not working I'm happy to take a look.

Patrick

Hi, patrick, the following is my va module:

`include "disciplines.vams"
`include "constants.vams"

module divider4 (out, in);

input in;
output out ;
electrical in, out;

parameter real vlo=0;
parameter real vhi=1.2;
parameter real vth = (vhi+vlo)/2;
parameter integer dir=1 from [-1:1] exclude 0;
parameter real trf=100p from (0:inf);
parameter real td=0 from [0:inf);
parameter real ttol=1p from (0:inf);
parameter integer ratio=4;

integer count, n;

analog begin

@(cross(V(in) - vth, dir, ttol)) begin
count = count + 1;
if (count >= ratio) count = 0;
end

n = (2*count >= ratio);
V(out) <+ transition(n ? vhi : vlo, td, trf);
end
endmodule

Even I simulated just two inverters with/without this va module, I got different results too!~ Embarrassed

You can try to simulate any circuits module with this va module.

Of course, the difference is not obvious in this simple circuit. But with more complex circuits, the difference would more and more obvious.

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icsoul

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Re: About mix simulation for verilog-a and HSPICE
Reply #13 - Oct 15^th, 2008, 7:43pm

Geoffrey_Coram wrote on Oct 15^th, 2008, 5:25am:

Did you use $bound_step and $discontinuity ?

I still don't understand what could go wrong in icsoul's scenario where he just had the .hdl statement and no instance of the object ...

No, I didn't use those features.

I'm confused, it is unreasonable at all.

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patrick Junior Member Offline Posts: 30 Santa Rosa, CA.	Re: About mix simulation for verilog-a and HSPICE Reply #14 - Oct 15^th, 2008, 10:11pm Can you run your simulations with the "runlvl" option turned off?, .option runlvl=0 and see if you still see changes with/without VA.
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