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About mix simulation for verilog-a and HSPICE (Read 12540 times)

Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: About mix simulation for verilog-a and HSPICE Reply #15 - Oct 16^th, 2008, 9:49am @cross can act to control the timestep, also, which could have some effect on the simulation.
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icsoul Junior Member Offline Posts: 29	Re: About mix simulation for verilog-a and HSPICE Reply #16 - Oct 17^th, 2008, 5:13am patrick wrote on Oct 15^th, 2008, 10:11pm: Can you run your simulations with the "runlvl" option turned off?, .option runlvl=0 and see if you still see changes with/without VA. I have tried this option, but it has no help.
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icsoul Junior Member Offline Posts: 29	Re: About mix simulation for verilog-a and HSPICE Reply #17 - Oct 17^th, 2008, 5:22am Geoffrey_Coram wrote on Oct 16^th, 2008, 9:49am: @cross can act to control the timestep, also, which could have some effect on the simulation. Hi, Geoffrey_Coram Could you give some advice to avoid this effect?
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Geoffrey_Coram

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Posts: 1999
Massachusetts, USA

Re: About mix simulation for verilog-a and HSPICE
Reply #18 - Oct 17^th, 2008, 7:35am

icsoul wrote on Oct 17^th, 2008, 5:22am:

Could you give some advice to avoid this effect?

That's sort of a paradoxical request: the cross event is specifically intended to control the timestep such that the crossing time is accurately resolved.

You could change the code so that it samples the voltage and determines for itself whether a rising or falling edge has occurred, but you run the risk of missing an edge.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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icsoul Junior Member Offline Posts: 29	Re: About mix simulation for verilog-a and HSPICE Reply #19 - Oct 21^st, 2008, 9:36pm I got a new version HSPICE and the problem is solved. Thank all of you! icsoul
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