The Designer's Guide Community
Forum
ForumVerilog-AMSAnalysisModelingDesignTheory
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Oct 28th, 2024, 3:52pm
 
  HomeHelpSearchLoginRegisterPM to admin    
The Designer's Guide Community Forum › Design › Analog Design › freuency devider
‹ Previous topic | Next topic ›
Pages: 1
Send Topic Print
freuency devider (Read 1028 times)
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
freuency devider
Oct 14th, 2008, 10:12pm  
hi,
   can any body please tell me is there any way to divide the frequency of sinusoidal  signals, and multiplying clk frequency ( not with PLL)
Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
Pages: 1
Send Topic Print
‹ Previous topic | Next topic ›
« Home ‹ Board
The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.