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Tareeq

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VCO buffer: any suggestions ?
Oct 18^th, 2008, 4:19pm

Hi All,

This post is the next episode in my VCO design (which started by "speculations" on flicker noise coefficient)

Well, I ve finally chosen and all pmos LC VCO architecture, Pmos bias current source, Pmos negative gm, and Pmos varactors .

The resulting signal is differential - oscillating (Hmmm.. that's the goal right Wink

) - between [-1.2V and 1.2V] approximately.
Willing to isolate the output of my VCO while preserving its good performances, I consider a second stage where the signal [-1.2;1.2] would be regenerated into the [0-2.5] voltage domain.

I propose something like (vco_outp => vco_outp_buffered) : http://ess000.free.fr/vco+buffer.jpg

With decoupling capacitor and center tap inductor pin to vdd12

Your comments and suggestions/ other alternatives are welcomed.

Tareeq.

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« Last Edit: Oct 18^th, 2008, 6:34pm by Tareeq »

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Tareeq Junior Member Offline Posts: 14	Re: VCO buffer: any suggestions ? Reply #1 - Oct 18^th, 2008, 7:02pm Perhaps adding a shunt resistance could be an option since bandwidth and linearity is increased together with low output impedance....
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: VCO buffer: any suggestions ? Reply #2 - Oct 20^th, 2008, 3:45am Do you need to set the input DC bias for the VCO buffer?
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Tareeq Junior Member Offline Posts: 14	Re: VCO buffer: any suggestions ? Reply #3 - Oct 20^th, 2008, 5:39pm I guess so, yes..sorry I should bias the nmos with sufficent current to sustain the bandwidth, that's one missing point...
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Tareeq

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Re: VCO buffer: any suggestions ?
Reply #4 - Oct 29^th, 2008, 10:24pm

When doing an sp analysis at the output of the VCO (assuming no buffers are connected), it has a real and imaginary part. In this case:

- Should we arrange a matching network (just like in LNAs) at the input of the buffer ?

- In case a reduction of the output amplitude of the VCO is desired, can't we make an impedance MISmatch ? in that case, the reflected wave could disturb the VCO right ?

Your comment about these unclear issues are most welcomed. Thanks.

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aaron_do

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Re: VCO buffer: any suggestions ?
Reply #5 - Oct 30^th, 2008, 10:42pm

Hi,

VCO output is a large signal, but SP analysis is small signal. So i don't think it would work. Even if it were small signal, why does your buffer have an input resistance anyway?

Also, i'm not very experienced with VCO design, but i suspect your VCO output impedance should not have an imaginary part or a real part. When it is oscillating, both the real and imaginary part of the output impedance should be zero. Correct me if i'm wrong...

cheers,
Aaron

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there is no energy in matter other than that received from the environment - Nikola Tesla

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didac

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Re: VCO buffer: any suggestions ?
Reply #6 - Oct 31^st, 2008, 12:56pm

Hi,
I agree with Aaron that sp it's not providing the correct results, it's taking the DC point and calculating some impedance but not oscillation it's built.
For your second question if you have a reflected wave it will affect the VCO operation, I suppose that will be something similar to injection locking-not sure-, but wether you have a reflected wave or not depends if you have a transmission line between your VCO and your buffer(so it depends on your operating frequency, the distance between buffer and VCO).
Looking at your drawing maybe it would be more dangerous the magnetic coupling between the VCO and buffer coils.
Hope it helps,

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Tareeq

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Re: VCO buffer: any suggestions ?
Reply #7 - Oct 31^st, 2008, 3:40pm

First of all, thank for your respective feedback.

Although sp analysis might be suitable within the framework of LNA impedance matching dealing with an input signal flirting with the noise level, I acknowledge that the situation of VCO's is rather different. This point is taken.

To Aaron: I agree with you, ideally the impedance should be zero except a little epsilon in the real part due to possible mismatching between the negative gm and esr resistance of the capacitor and the inductor (BTW I am not a vco expert either).

In that case, a decoupling capacitor should ensure that @ 5Ghz, Zc <<1,

To Didac:
You seem to suggest that impedance matching is something to consider only in the case of transmission lines shouldnt be something to consider between any cascaded consecutive stages ??
Your warning against magnetic coupling is certainly something to care about. thanks.

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aaron_do

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Re: VCO buffer: any suggestions ?
Reply #8 - Oct 31^st, 2008, 5:55pm

Hi,

Quote:

You seem to suggest that impedance matching is something to consider only in the case of transmission lines shouldnt be something to consider between any cascaded consecutive stages ??

In CMOS, the shunt gate resistance is very large. So you can't really match to it. In inductive degeneration, we deliberately add series resistance (i.e. reduce shunt resistance) in order to make matching possible.

In general, signal reflection etc is only considered when the line that the signal is traveling on is a transmission line. On chip connections are too short compared to the wavelength of the signal to be considered transmission lines. For example, the wavelength at 3 GHz is approximately 10 cm. In general, you only need matching at the LNA (as far as i know).

Bare in mind that you can still use an LC network to step up or step down the signal. However, it doesn't need to be matched, and it will also add loading to either side of the network.

cheers,
Aaron

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there is no energy in matter other than that received from the environment - Nikola Tesla

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didac

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Re: VCO buffer: any suggestions ?
Reply #9 - Nov 1^st, 2008, 6:45am

Hi,
Typically you don't worry too much about transmission lines on-chip for the reasons explained by Aaron, the critical length it's about 1/16 to 1/10 of the wavelength(that it's determined by the medium and the line geometry through effective relative dielectric constant). If you surf up a little bit IEEE website you will see that people doesn't worry about transmission lines in silicon IC's until 30GHz more or less.
Hope it helps,

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ACWWong

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Re: VCO buffer: any suggestions ?
Reply #10 - Nov 2^nd, 2008, 7:07am

didac wrote on Nov 1^st, 2008, 6:45am:

Hi,
Typically you don't worry too much about transmission lines on-chip for the reasons explained by Aaron, the critical length it's about 1/16 to 1/10 of the wavelength(that it's determined by the medium and the line geometry through effective relative dielectric constant). If you surf up a little bit IEEE website you will see that people doesn't worry about transmission lines in silicon IC's until 30GHz more or less.
Hope it helps,

agreed, you don't usually care up until about 1/10 of the wavelength, but that is easily achievable with on chip geometries, especially when one considers the harmonics of the oscillation frequency. So even with a say a 5GHz VCO, you should really be interested in layout transmission effects for frequency of 10GHz & 15GHz ....

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