Hi All,
This post is the next episode in my VCO design (which started by "speculations" on flicker noise coefficient)
Well, I ve finally chosen and all pmos LC VCO architecture, Pmos bias current source, Pmos negative gm, and Pmos varactors .
The resulting signal is differential - oscillating (Hmmm.. that's the goal right
![Wink Wink](https://designers-guide.org/forum/Templates/Forum/default/wink.gif)
) - between [-1.2V and 1.2V] approximately.
Willing to isolate the output of my VCO while preserving its good performances, I consider a second stage where the signal [
-1.2;1.2] would be regenerated into the [0-2.5] voltage domain.
I propose something like (vco_outp => vco_outp_buffered) :
http://ess000.free.fr/vco+buffer.jpgWith decoupling capacitor and center tap inductor pin to vdd12
Your comments and suggestions/ other alternatives are welcomed.
Tareeq.