Unlike pipelined ADCs where there are very clear guidelines on the gain (and settling accuracy requirement) of the opamps, there are no clear conditions for delta-sigma ADCs.

1. Some texts claim that DC gain and finite settling accuracy are no issue as long as settling is linear. The caveat is that linear settling is almost impossible to guarantee. One could use a pure class-AB kind of design which has an almost linear settling (no slew limiting) and get quite good linearity for normal signals, but what happens when we add shaped quantization noise?

2. Use of the feedforward structure should be better than feedback in the modulator because one then processes only shaped quantization noise in the first integrator at least. So this needs less precision. However, the shaped noise must also not get intermodulated and appear in the baseband. So what is the minimum required settling accuracy at the input of the opamp for a given dynamic range target?

Typically, I follow the rule that everything ought to settle to atleast as much precision as the required dynamic range in the first integrator to ensure that no shaped noise gets modulated down to the baseband even in a feedforward structure, and that there are no other parasitic effects such as supply dependence etc.

But what is the actual requirement? Can someone please enlighten me?

Regards,
Vivek

Hi Berti,

I am not quite convinced by this explanation of yours.

It is clear to me that if there are charge-taking nonidealities or reference modulation, then there is plenty of trouble to expect.

However, I am simply worried about the manner in which the shaped quantization noise is processed by the loop filter, assuming that we use a feedforward structure and no net signal enters the first integrator inputs.

As the shaped noise is basically a broadband noise and a first integrator with finite gain and slew rate is a nonlinear block, we will likely to see every order of intermodulation on the components of this broadband noise, many of which find their way into the baseband.

As for reducing bias currents in measurement setups, there is always the question of which process corner you were sitting at with the measured chip. Usually, the first runs are centered at the typ corner which means that that settling accuracy of the opamps is probably quite a bit better than in the worst cases, maybe as much as 10-20 dB. So, I would not be surprised if you could reduce the bias current 10-20% without adverse effects for a well-designed device. If on the other hand, it is possible to cut down bias current by much more for a design which followed a conservative approach, then there might be something in it.

I will need to look through this reference (Balmelli). There seems no soft copy online, but the abstract talks about achieving 14b resolution for broadband conversion. Let me try to see if I can get hold of it.

Regards,
Vivek

Hi Berti,

Sure! delta-sigma converters are quite robust against process/temp variation as far as the basic functionality and transfer function are concerned, but as far as settling requirements on the opamps go, I would imagine that there is a minimum settling requirement which needs to be guaranteed to achieve proper SNR and THD.

As you correctly said, this would lie somewhere below the conservative limit for opamp settling which assumes settling accuracy >= desired dynamic range. What would interest me would be your estimation of the lower end of this scale.

Could you comment on the kind of levels one may allow the settling accuracy to drop down to without problems? Let's assume a feedforward structure with no net signal at the input or output of integrator # 1, a target dynamic range say 90 dB. Can I make my design with just 60 dB linear integrator # 1? If I were using a pure class-AB topology with slew time independent of signal input and assuming operation within a band where the signal swing does not cause opamp gain to deviate from nominal by more than 1 dB, then I may rest easy. But what happens if slewing causes the settling accuracy to vary more, say best case settling accuracy for medium level signals is about 10 dB-20 dB better than settling for peak signals (all at output of integrator # 1)?

I would be interested in your answer.

Regards
Vivek

Tlaloc wrote on Oct 29^th, 2008, 9:19am:


Hi,

I agree with you that the noise spec is going to be decide the current, but that will be the minimum current you are going to need. However, consider the statement one encounters so often in the literature (and for which I am yet to find a convincing explanation) that one can do with a 60 dB gain opamp and still achieve 90 dB dynamic range. Of course, if the opamp were ideal (true first-order system with no slew limitation), this would be true. But there are no such opamps, atleast none that fulfil the requirement perfectly.

So I have been making mine to achieve 1/2 LSB settling. A 90 dB settling however requires a bandwidth 1.5x better than a for a 60 dB case, which will need atleast 1.5x more current. Moreover, we know that with a suitable modulator architecture such as CIFF, the requirements on the opamp settling can be reduced considerably. So designing for 1/2 LSB settling is too conservative and wasteful.

That's why I might have given the impression that I consider an AB stage as an inevitability. Of course there are other issues in real design too. Maybe I will have to make a more detailed model to figure out what gain (or in other words, settling accuracy) I need.

Regards,
Vivek

Tlaloc wrote on Oct 30^th, 2008, 12:18pm:


Agree that there is some tradeoff between the slewing performance and noise on supply. After all, in the limit, there are digital inverters which have slew rates limited purely by supply resistance but generate noise. Any class-AB circuit will also generate this noise, while class-A will keep it more or less quiet.

Tlaloc wrote on Oct 30^th, 2008, 12:18pm:


It is unfair to ask for the same settling performance from a class-AB as from a class-A, especially given the design overhead for it, and also because a good class-AB would in principle free the designer from requiring 1/2 LSB settling since the slewing time is independent of the signal level, and hence the settling is really linear to a very good approximation. A better point to raise might have been noise. There are 2 points here:

1. Since the class-AB design must support a wide range of currents, your active loads will be designed suboptimally generating more noise than what you want.

2. Since the quiescent current will be much less than in a class-A, the noise contribution of the opamp will be higher.

However, we are getting away from the discussion. I am still not sure what settling requirements to choose. Anything more on this?

Regards,
Vivek

Hi Berti,

Yes, settling speed is influenced by the closed-loop bandwidth, but settling accuracy also depends on the overall loop gain. An opamp with DC gain of 40 dB will not settle (at its inputs) to better than 40 dB no matter how much time you give it, or how fast you make it.

What I meant with my statement was that if you manage to make the opamp close to first-order (transient response not limited by finite slewing), and if your circuit does not actually require a very high DC gain (unlike the case for say the opamp in a pipelined ADC), then you can achieve much higher dynamic range.

Class-A is OK for a number of reasons, esp. the noise and disturbance related ones mentioned in earlier posts here. However, I am not sure if I agree with your statement that one can easily reduce signal swings to small enough values to eliminate slewing. This would entail the following:

1. You would either need to limit input signal to the system to small values => poorer SNR.

2. You would use very large integration caps. So, voltage swing is reduced but to a first-order approx., the net charge to be delivered by the opamp remains the same (CdV), => for a given power consumption, your class-A slew rate is now reduced by the same factor by which you reduced the signal swings.

3. If you reduce the swing too much, then the effective gain of the integrator drops, => noise from later stages becomes that much more significant. Whether it also becomes critical depends of course on how much you reduce the swing by and the OSR.

I agree with the rest of your points that quantization noise is usually non-dominant. However, the issue here is whether that quantization noise will fold into the baseband due to nonlinear settling artifacts (slewing) in the opamp. A differential scheme should go a long way in helping here as you correctly mentioned earlier, but the question is: how much settling accuracy is needed for a given dynamic range at the end of the day, assuming we have/do not have slewing.

Regards,
Vivek

Berti wrote on Nov 5^th, 2008, 10:24pm:


Hi Berti,

This is precisely the point. Of course, the main requirement is the linearity. The question is what level of linearity is needed. For a pipelined ADC, the requirement is very easy. However, the required linearity for delta-sigma modulators (and hence the DC gain, and the accuracy to which the opamp inputs approximate the virtual ground at the end of the allocated time) is not so easy to estimate. It lies somewhere below the requirement which an equivalent pipelined ADC would have, and is mainly limited by the fact that nonlinearities in processing the signal + shaped noise can cause some shaped noise to mix down to the baseband as far as I can see from my simulations. THD on the input signal comes into play only later.

Of course, I can run several simulations with opamp models which account for finite gain, finite slewing, finite bandwidth but it is always good to have some basis figure for reference to know what gain and settling accuracy I need to target, particularly when doing system level estimations for things like power consumption. As I mentioned earlier, if I only needed my opamp inputs to settle to 60 dB precision instead of 90 dB, I potentially can save 30% current. And if there are structures like the feedforward one where the requirements on the opamp are lower, then I would rather use those.

I just want to quantify the required precision.

Sadly, multibit is not an option in every case.

Regards,
Vivek