Hi Julian,
1- Start with the Pi model of the inductor modelling all kind of parasitic effect of the inductor in terms of capacitance and resistance. And give it reasonable values so that, when you shall optimize the inductance with asitic things would be just ready (Documentation of asitic and Pi model available here
http://rfic.eecs.berkeley.edu/~niknejad/asitic.html)
2- The fact that you dont see anything could means two things:
2a :That the gm of the transistor is not big enough , therefore increase either or both the width and the bias current
2b :Not any transient parameter can make simulation work. You have to be careful. Set: reltol to 10-5, vabstol 10-8, iabstol -13
Select gear2only for the integration method, select "alllocal" for increased acuracy, and gmin reasonably low (10-14).
Also you can use nodeset for initial condition and put an initial voltage higher than the expected common mode of the output signals.
Also, what is the value of the potential VSSD ?