ywguo
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Hi jlee,
I assume you mean a CMOS divider, spicifically it is a CML/SCL divider with resistor load, a divider-by-2.
It reaches the maximum clock rate when the clock period approaches the RC time constant. At that tme, the divider fails.
It has a minimum clock rate because the the circuit will oscillate if the the clock rises/falls slowly.
Please refer to Ullas Singh and Michael Green, Dynamics of High-frequency CMOS Dividers, ISCAS 2002, for the details.
Yawei
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