Hi jlee,

I assume you mean a CMOS divider, spicifically it is a CML/SCL divider with resistor load, a divider-by-2.

It reaches the maximum clock rate when the clock period approaches the RC time constant. At that tme, the divider fails.

It has a minimum clock rate because the the circuit will oscillate if the the clock rises/falls slowly.

Please refer to Ullas Singh and Michael Green, Dynamics of High-frequency CMOS Dividers, ISCAS 2002, for the details.


Yawei

Hi jlee,
  The problem is similar to the one in digital synchronized circuits. If the clock frequency is high, there will exist setup-up time violations. When the clock frequency is slow, hold-up time is important.
  Please check the critical paths of each DFFS in your CML/SCL dividers.
  Good Luck!

zwtang