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Process insenstitive delay cell (Read 8302 times)

smarty

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Posts: 46

Process insenstitive delay cell
Nov 11^th, 2008, 7:22am

Hi all,
� �I wanted to have a process insensitive delay cell. Is there any way we can achieve this. I tried with current starved inverter and thought of controlling the delay with current, but I am unable to achieve delay insensitive to process variation or minimal variation with process.
Can anybody suggest, whether we can achieve the delay insensitive to process variation, if so whether I can get anything in literature.

Thanks and Regards,
SBR

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Berti Community Fellow Offline Posts: 356	Re: Process insenstitive delay cell Reply #1 - Nov 12^th, 2008, 12:56am Sure, a delay-locked loop (DLL) can be design to serve as a process-independent delay-line. Cheers
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smarty Community Member Offline Posts: 46	Re: Process insenstitive delay cell Reply #2 - Nov 12^th, 2008, 1:02am Thanks Berti. I know this should sound a bit vague, but in any way can we control the delay of a cell over PVT if the delay cell is operate in open loop?. Thanks and Regards, SBR
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Berti Community Fellow Offline Posts: 356	Re: Process insenstitive delay cell Reply #3 - Nov 12^th, 2008, 7:09am I don't know. At least the temperature dependence can probably be reduces when using a PTAT current. Cheers
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smarty Community Member Offline Posts: 46	Re: Process insenstitive delay cell Reply #4 - Nov 12^th, 2008, 7:36am Thanks Berti... What I thought was (quite possible I might be wrong also) by using a controlled delay element, like current controlled delay element or VCDL(voltage controlled delay cell), we could achieve reducing the process variation of the delay. Do you have any thought regarding this. Thanks and Regards, SBR
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Berti Community Fellow Offline Posts: 356	Re: Process insenstitive delay cell Reply #5 - Nov 13^th, 2008, 6:08am Sure, but the generation of the control-current (or voltage) that compensates the delay variation will be the real challenge. Cheers
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smarty Community Member Offline Posts: 46	Re: Process insenstitive delay cell Reply #6 - Nov 13^th, 2008, 7:42am Thanks Berti.. I am finding hard as you suggested in generating the control. With your experience can you suggest any trick by which we can get the control work as needed. Thanks, SBR
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fonseca.ha

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Posts: 28
UK

Re: Process insenstitive delay cell
Reply #7 - Nov 16^th, 2008, 9:31am

Hi. What is the aplication?

A very accurate way to delay signals by a controled ammount is having a master DLL that generates a control voltage.

After that, the control voltage can be used on a "Slave" delay line in open loop.

A simplier way is if the DLL is digital but you may end up with more jitter.

Another way could with the following:
Using the Band Gap Voltage and a Switched Capacitor Resistor To generate a current.
After use that current (I) to charge a capacitor. The ramp I/C depends only on the ratio of capacitors! so it can be quite accurate!

Alternativelly
Do you have access to a well defined reference current. Perhaps by using an external resistor?

Cheers,
H

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loose-electron

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Re: Process insenstitive delay cell
Reply #8 - Dec 5^th, 2008, 1:56pm

This has been done many times with a PLL or DLL - You have two delay paths, one in the PLL/DLL and the other in the delay path that you are trying to control.

the two delay blocks sit close to each other (same process/temperature conditions) and connect to the same power (same power voltage conditions)

The delay of both the PLL/DLL and the Delay Path are under control of the PLL/DLL feedback system. The PLL/DLL is connected to a reference clock and set to get the desired VCO(PLL) or Delay Line (DLL) time delay needed.

The control voltage tracks out the PVT effects, and you are done.

-- Jerry

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	Re: Process insenstitive delay cell Reply #9 - May 6^th, 2009, 10:48am I guess Mr. Smarty is looking for a design which generate a delay like 1ns without using any know reference clock frequency or reference of timing delay. And he wished to have small variation from process skew and voltage/temperature change. Right?
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smarty Community Member Offline Posts: 46	Re: Process insenstitive delay cell Reply #10 - May 31^st, 2009, 8:27am All, �Sorry for not able to reply in advance as I was away and had not checked this. But yes what Mr. Neoflash is saying is to an extent correct. I was trying to generate a delay for which I do not have any reference clock with minimal PV variation. Thanks, SBR
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