wwwww12345
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Posts: 7
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I knew the reason now. I changed the data type of "relay " to "integer" and the problem is solved. But the question again comes out that how can I compare a 2-bit bus? such as in the code below, it still cannot work well:
module caseinveriloga2(A1,A2,A3,A0,S1,S0,OUT);
// 2-4 MUX
output OUT; electrical OUT; input A1,A2,A3,A0,S1,S0; electrical A1,A2,A3,A0,S1,S0;
integer relay[1:0];
parameter real vth=0.5; parameter real vhigh=1; parameter real vlow=0;
analog begin
relay[0] = (V(S0) > vth) ; relay[1] = (V(S1) > vth) ;
case (relay) 00: V(OUT) <+ transition (V(A0), 1n, 50p); 01: V(OUT) <+ transition (V(A1), 1n,50p); 10: V(OUT) <+ transition (V(A2), 1n,50p); 11: V(OUT) <+ transition (V(A3), 1n,50p); endcase end
endmodule
I guess the reason why I am wrong is that "relay" cannot equal "00","01", etc. Anyone can help me ? thank you!
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