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why my D-ff always outputs low voltage?
Dec 10^th, 2008, 8:22pm

Hi all,
I wrote a verilogA code using "case" for I want to use case sentence in other complex cell. So I wrote a simple DFF as practice.
The code is as follows:

module caseinveriloga(vpa,in,clk);

output vpa;
electrical vpa;
input in,clk;
electrical in,clk;
//output relay;
//electrical relay;

real relay;

parameter real vth=0.5;
parameter real vhigh=1;
parameter real vlow=0;

analog begin
@(cross(V(clk) - vth, +1) or initial_step)

relay = (V(in) > vth) ;

case (relay)
0: V(vpa) <+ transition (vlow, 1n, 50p);
1: V(vpa) <+ transition (vhigh, 1n,50p);
default : V(vpa) <+ transition (vhigh/2, 1n,50p);
endcase
end
endmodule

I send clock and data in every phase, but the output is always low voltage. Who can tell me what is wrong in this code ? Thank you in advance!

BTW, Could anyone tell me how to output a result after 2 clock edge? Thanks !

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wwwww12345

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Posts: 7

Re: why my D-ff always outputs low voltage?
Reply #1 - Dec 10^th, 2008, 9:43pm

I knew the reason now. I changed the data type of "relay " to "integer" and the problem is solved. But the question again comes out that how can I compare a 2-bit bus? such as in the code below, it still cannot work well:

module caseinveriloga2(A1,A2,A3,A0,S1,S0,OUT);

// 2-4 MUX

output OUT;
electrical OUT;
input A1,A2,A3,A0,S1,S0;
electrical A1,A2,A3,A0,S1,S0;

integer relay[1:0];

parameter real vth=0.5;
parameter real vhigh=1;
parameter real vlow=0;

analog begin

relay[0] = (V(S0) > vth) ;
relay[1] = (V(S1) > vth) ;

case (relay)
00: V(OUT) <+ transition (V(A0), 1n, 50p);
01: V(OUT) <+ transition (V(A1), 1n,50p);
10: V(OUT) <+ transition (V(A2), 1n,50p);
11: V(OUT) <+ transition (V(A3), 1n,50p);
endcase
end

endmodule

I guess the reason why I am wrong is that "relay" cannot equal "00","01", etc. Anyone can help me ? thank you!

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Ken Kundert

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Posts: 2386
Silicon Valley

Re: why my D-ff always outputs low voltage?
Reply #2 - Dec 10^th, 2008, 10:59pm

You should almost never put transition functions inside a conditional statement. In addition, you should never use a node voltage as the argument of a transition function.

So you probably need something like ...
real x;
case (relay)
00: x = V(A0);
01: x = V(A1);
10: x = V(A2);
11: x = V(A3);
endcase
V(OUT) <+ x;

If you want to switch smoothly between the four signals, then you should use something like this ...
real m0, m1, m2, m3;
m0 = 0;
m1 = 0;
m2 = 0;
m3 = 0;
case (relay)
00: m0 = 1;
01: m1 = 1;
10: m2 = 1;
11: m3 = 1;
endcase
V(OUT) <+ V(A0)*transition(m0, 1n, 50p)
+ V(A1)*transition(m1, 1n, 50p)
+ V(A2)*transition(m2, 1n, 50p)
+ V(A3)*transition(m3, 1n, 50p);

-Ken

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wwwww12345 New Member Offline Posts: 7	Re: why my D-ff always outputs low voltage? Reply #3 - Dec 14^th, 2008, 11:16pm Thank you! Ken! I have solved the problem based on your code.
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