I would say that depends on your requirement!
If you intend to write an ideal transmission switch model, just to get the functionality and use
it in another design for verifying the bigger design then it's pretty simple.
Use something like..

@(cross(V(en) -threshold,+1))
               ;
if(V(en) > threshold)
        V(in,out) <+ 0;                  ..... (1)
else
        I(in,out) <+ 0;                    ......(2)
for one of the switches. Similarly for the other switch of your transmission gate..write
a similar code. Well, this could be your  simple switch model!!
It;s better to use some finite on resistance in (1) and off resistance in (2). This makes
the model more realistic and might avoid all those nasty convergecne issues! If you
are using Verilog-AMS then you can treat the enable as a digital signal and write it
as if(en). Check   for the currect syntax.

But, if you want to model other features of transmission gate, such as input cap, output cap etc.
then you need to keep adding to this simple model. For example, you may like to use slew to model
the finite slew rate associated with any realistic switch. Also, your CMOS Tx will have some
drops across the switch due to finite threshold voltages of the mos!! There's a sea of things you might like to model!! Hope it helps!

Rajdeep