loose-electron
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Posts: 1638
San Diego California
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Frequency pulling like this is a bit iffy.
1. The simple single inverter oscillator structure in CMOS is a very inefficient structure. As an example, to get sufficient gain over corners, the geometry needs to be pushed up in size quite a bit. It's an I/O cell so it ends up being pretty big as it is.) That geometry increase causes a huge variance in static DC current. Over PVT corners in 45nm TSMC CMOS and 2db of open loop gain margin the current varies from about 80uA to 12mA - Huge!
2. Frequency pulling of a crystal, is stongly dependent on the Q of the crystal. You may want to look at the extremes of the stand alone crystal accuracy, and the requirements of your real time clock. The structure as illustrated reduces the gain of the loop and not much else.
3. What comes out of a crystal is a sinusoid, without harmonic content. The pulling circuit shown will largely just reduce the sinusoind amplitude. Need a low Q to work well, and most crystals are 10E4 to 10e5 in Q.
There are some papers out there on crystal pulling, need to do some research there.
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