Hey all,

1- Why are Cadence simulation tools made to work on Linux only and not Windows?

2- I am using a 0.13um UMC design kit. This means that typically the minimum transistor length I can get is 0.13u but actually it is 0.12u. And I'm sure the design kit is a 0.13u and not a 0.12u tech kit because this is what is written in the user's manual of the kit.

2. The UMC 0.13um PDK has a minimum gate length (as entered into the design system) of 0.12um.
The "discrepancy" between the enterable minimum gate length of a particular PDK and the headline technology node is commonplace. So a 0.13um technology node will have a minimum enterable gate length of anything between say 0.11um to 0.15um depending on the foundry.