wave
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Andrew - thanks for the reply on .cdb files. Very useful.
I actually asked Mr. Spectre himself look at the code a bit and he narrowed it down to this region. Vreg is within our tolerance limits, but something is sequenced (initial conditions) in the simulator to catch vreg_ok=0.
I guess there are more robust ways to write this for OSS. How specifically, I'm not sure...
regards, Wave
//-- vreg
always @(above(V(vreg,vssa) - vreg_min)) begin vreg_ok = 1; if(debug) $strobe("%t: %m: vreg_ok = %0b", $realtime, vreg_ok); end // vreg > vreg_min
always @(above(-1.0*(V(vreg,vssa) - vreg_min))) begin vreg_ok = 0; $strobe("%t: %m: vreg has fallen below . vreg_min = %e", $realtime, vreg_min); end // vreg < vreg_min
always @(above(V(vreg,vssa) - vreg_max)) begin vreg_ok = 0; $strobe("%t: %m: ***WARNING*** vreg has risen above vreg_max. vreg_max = %e", $realtime, vreg_max); end // vreg > vreg_max
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