Hi,

I have the option of using high-speed NPNs instead of NMOS devices for a high-speed and high-accuracy pipelined ADC design. How can I take advantage of these devices? Some points come to my mind, but I would be glad if someone with experience in using BJTs in such designs could comment:

1. Could potentially use as input devices in opamp but base current poses a problem. The summing node will not be high ohmic anymore, need some compensation but this will not work perfectly, can expect problems due to this. Any base current compensation will also add considerable noise.

2. Can make 2-stage amps and use the NPN in the second stage to push out the pole, but then the first stage needs PMOS transistors (=> possibly smaller Gm and higher noise from NMOS active load).

Would there be a big advantage of the BJT ? Feedback welcome.

Vivek

Hi Tosei,

Thanks a lot for your response. Please see my comments below:

HdrChopper wrote on Jan 29^th, 2009, 5:32pm:


Indeed, 1/f noise reduction would be achieved very nicely with BJTs, but mostly, this is not a very big issue in wideband pipelined ADCs as the thermal noise dominates much more, offset is usually also not a big problem. Of course, it is always nicer if you don't need to do autozeroing just for removing offset and 1/f.

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I meant that the extra branches added for base current compensation would increase the noise. Of course, the noise is probably not increased a lot, but I would expect that the base current compensation network needs to have a very high bandwidth if I use it in a pipelined ADC because this must also settle quickly. So, this runs off more current and injects more noise at the opamp input. Or am I mistaken?

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Yes! this is the issue. I know that for lower resolutions like 10 bits or so, people have managed to get away with the residual errors from the base current but I am not sure what can be done for higher resolution levels.

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Ah! but you cannot make a pipelined ADC with CT stages.

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You mean that the N-side active load and cascode devices are realized with NPN. This of course needs less headroom but is terribly noisy, because BJTs always have Gm=Ic/Vt, which is the exact opposite of what one wants in active loads. I think the real advantage would be if one could use BJTs where higher Gm is needed.

Quote:


True, but maybe there is some way to optimize things. I see 2 advantages of using NPN as the second stage Gm: (1) Higher Gm for lower current and 2nd pole is pushed out easily. (2) RHP zero is avoided or atleast made insignificant with a BJT, making compensation easier. The disadvantage as I already wrote is that one needs to use a PMOS for the input of the 1st stage, which is slower and noisier (due to usually larger Gm of its NMOS active load).

Nonetheless, thanks a lot. If I can figure out a good way to overcome the base current issue (that's what haunted all those who tried to use BJTs in switched-cap filters and forced them to move to MOS where that works naturally).

Maybe I should not try to make SC circuits with BJTs.

Regards,

Vivek

Hi everyone,

Thanks for your response.

I am not using 90 nm CMOS and I have MOS gates which don't leak at all. It is one
of the older processes. 1/f noise is also not a big issue as the wide bandwidth requirement on my ADC translates to a much higher white noise than 1/f. Offset is not critical.

I have basically the choice between using the standard CMOS process, or an enhanced version with super-fast BJTs in addition. If I could get significant benefits in terms of power consumption or ease of design, I might consider using the BJTs.

It would seem to me that there is not a very big gain in using BJTs in this case.

Tosei: I need to see if base-current compensation works well for me. Could you kindly post a link showing what method you use for this? Is this the standard textbook method?

Jerry: I think the availability of good buffers (in form of BJT source followers) may be useful in providing a front-end free of the usual switching capacitor although I need to look carefully at the noise and headroom penalties associated with this.

Best regards,

Vivek

loose-electron wrote on Feb 10^th, 2009, 8:55pm:


Hi Jerry,

I agree with you that the wafers would cost less and of course I myself would use just MOS. However, the question of interest here is whether the use of a BJT would allow enough improvement in performance/power consumption for a high-perf. ADC (think 14-16 bits, few Msps or so) that one may consider using them. If there is a significant technical advantage (and maybe we can even add some good functions upfront like a good input buffer for the device, then maybe the cost does not look so bad at the end.

For me, it is not clear what impact the use of the BJT base current (remaining current after base current compensation) has on high-accuracy switched-cap circuits.

Regards,

Vivek

P.S.: We have our own foundry and so it does not cost an arm and a leg even to add RF BJTs

Hello Vivek,

I think we attended the advanced analog design mead course in Lausanne a few years ago.  I hope you have been doing well since then.

I stumbled upon this thread and I have one comment that hasn't been brought up yet.

Please be careful with the bipolars if you use them as in my experience I have found that more effort is put into accurate cmos models and less effort into the bipolar models.

Good luck with your design,
Dan

Hi vivkr! I raided your parts box at OSU!

Hi Dan! I helped you design something!

Hi everyone else! Yes, I am procrastinating today!

Re BiCMOS, yes, bipolar can help. Higher gm, higher output impedance, faster mirrors. To give you some ideas look at the 2006 JSSC paper "A 100-dB SFDR 80-MSPS 14-Bit 0.35-μm BiCMOS Pipeline ADC"

Also, base current cancellation will at least double noise power since the current used to cancel the original base current is uncorrelated with the original base current.